SystemVerilog implementation for common 74xxx series ICs with testbenches
Chips implemented:
- 3-line to 8-line decoder / demultiplexer
Western: SN74LS138A/SN54LS138/SN54S138
USSR: K555ID7 / К555ИД7
- Quaduple 2 to 1 line selector/multiplexer
Western: SN74LS257
USSR: K555KP11/К555КП11
- Dual 4 to 1 line selector/multiplexer
Western: SN74LS253
USSR: K555KP12/К555КП12
- Quad 2 to 1 data selector / multiplexer
Western: SN74LS157
USSR: K555KP16 К555КП16
- D flip-flop
Western: SN74LS74
USSR: K555TM2/К555ТМ2
- Hex D-type flip-flops with clear
Western: SN74LS172
USSR: 555TM9/555ТМ9
- Presettable 4-bit binary up/down counter
Western: SN74LS193
USSR: 555IE7 / 555ИЕ7
- Synchronous 4-bit up/down binary counter
Western: 74LS169
USSR: 555IE17/555ИЕ17
- 4 bit fully synchronous binary counter
Western: 74LS163
USSR: K555IE18/К555ИЕ18