nmigen.lib: Add RoundRobin

nmigen/compat/genlib/roundrobin.py

@@ -0,0 +1,50 @@
+from ..._utils import deprecated
+from ..fhdl.module import CompatModule
+
+
+__all__ = ["RoundRobin", "SP_WITHDRAW", "SP_CE"]
+
+(SP_WITHDRAW, SP_CE) = range(2)
+
+@deprecated("instead of `migen.genlib.roundrobin.RoundRobin`, "
+            "use `nmigen.lib.roundrobin.RoundRobin`; note that RoundRobin does not "
+            "require a policy anymore, and that the `ce` attribute has been renamed"
+            "to `en`")
+class CompatRoundRobin(CompatModule):
+    def __init__(self, n, switch_policy=SP_WITHDRAW):
+        self.request = Signal(n)
+        self.grant = Signal(max=max(2, n))
+        self.switch_policy = switch_policy
+        if self.switch_policy == SP_CE:
+            self.ce = Signal()
+
+        ###
+
+        if n > 1:
+            cases = {}
+            for i in range(n):
+                switch = []
+                for j in reversed(range(i+1, i+n)):
+                    t = j % n
+                    switch = [
+                        If(self.request[t],
+                            self.grant.eq(t)
+                        ).Else(
+                            *switch
+                        )
+                    ]
+                if self.switch_policy == SP_WITHDRAW:
+                    case = [If(~self.request[i], *switch)]
+                else:
+                    case = switch
+                cases[i] = case
+            statement = Case(self.grant, cases)
+            if self.switch_policy == SP_CE:
+                statement = If(self.ce, statement)
+            self.sync += statement
+        else:
+            self.comb += self.grant.eq(0)
+
+
+
+RoundRobin = CompatRoundRobin

nmigen/lib/roundrobin.py

@@ -0,0 +1,54 @@
+from .. import *
+from functools import reduce
+from operator import or_
+
+
+__all__ = ["RoundRobin"]
+
+
+class RoundRobin(Elaboratable):
+    """Round-robin scheduler.
+
+    For a given set of requests, the round-robin scheduler will
+    grant one request.
+
+    Parameters
+    ----------
+    width : int
+        Number of requests.
+
+    Attributes
+    ----------
+    requests : Signal(width), in
+        Set of requests.
+    grant : Signal(range(width)), out
+        Number of the granted request.
+    valid : Signal(), out
+        Indicate if grant is valid.
+    """
+    def __init__(self, *, width):
+        if not isinstance(width, int) or width < 0:
+            raise ValueError("Width must be a non-negative integer, not {!r}"
+                             .format(width))
+        self.width    = width
+
+        self.requests = Signal(width)
+        self.grant    = Signal(range(width))
+        self.valid    = Signal()
+
+    def elaborate(self, platform):
+        m = Module()
+
+        with m.Switch(self.grant):
+            for i in range(self.width):
+                with m.Case(i):
+                    for pred in reversed(range(i)):
+                        with m.If(self.requests[pred]):
+                            m.d.sync += self.grant.eq(pred)
+                    for succ in reversed(range(i + 1, self.width)):
+                        with m.If(self.requests[succ]):
+                            m.d.sync += self.grant.eq(succ)
+
+        m.d.sync += self.valid.eq(reduce(or_, self.requests))
+
+        return m

nmigen/test/test_lib_roundrobin.py

@@ -0,0 +1,93 @@
+# nmigen: UnusedElaboratable=no
+import unittest
+from .utils import *
+from ..hdl import *
+from ..asserts import *
+from ..sim.pysim import *
+from ..lib.roundrobin import *
+
+
+class RoundRobinTestCase(unittest.TestCase):
+    def test_width(self):
+        dut = RoundRobin(width=32)
+        self.assertEqual(dut.width, 32)
+        self.assertEqual(len(dut.requests), 32)
+        self.assertEqual(len(dut.grant), 5)
+
+    def test_wrong_width(self):
+        with self.assertRaisesRegex(ValueError, r"Width must be a non-negative integer, not 'foo'"):
+            dut = RoundRobin(width="foo")
+        with self.assertRaisesRegex(ValueError, r"Width must be a non-negative integer, not -1"):
+            dut = RoundRobin(width=-1)
+
+
+class RoundRobinSimulationTestCase(unittest.TestCase):
+    def test_width_one(self):
+        dut = RoundRobin(width=1)
+        sim = Simulator(dut)
+        def process():
+            yield dut.requests.eq(0)
+            yield; yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 0)
+            self.assertFalse((yield dut.valid))
+
+            yield dut.requests.eq(1)
+            yield; yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 0)
+            self.assertTrue((yield dut.valid))
+        sim.add_sync_process(process)
+        sim.add_clock(1e-6)
+        with sim.write_vcd("test.vcd"):
+            sim.run()
+
+    def test_transitions(self):
+        dut = RoundRobin(width=3)
+        sim = Simulator(dut)
+        def process():
+            yield dut.requests.eq(0b111)
+            yield; yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 1)
+            self.assertTrue((yield dut.valid))
+
+            yield dut.requests.eq(0b110)
+            yield; yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 2)
+            self.assertTrue((yield dut.valid))
+
+            yield dut.requests.eq(0b010)
+            yield; yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 1)
+            self.assertTrue((yield dut.valid))
+
+            yield dut.requests.eq(0b011)
+            yield; yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 0)
+            self.assertTrue((yield dut.valid))
+
+            yield dut.requests.eq(0b001)
+            yield; yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 0)
+            self.assertTrue((yield dut.valid))
+
+            yield dut.requests.eq(0b101)
+            yield; yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 2)
+            self.assertTrue((yield dut.valid))
+
+            yield dut.requests.eq(0b100)
+            yield; yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 2)
+            self.assertTrue((yield dut.valid))
+
+            yield dut.requests.eq(0b000)
+            yield; yield Delay(1e-8)
+            self.assertFalse((yield dut.valid))
+
+            yield dut.requests.eq(0b001)
+            yield; yield Delay(1e-8)
+            self.assertEqual((yield dut.grant), 0)
+            self.assertTrue((yield dut.valid))
+        sim.add_sync_process(process)
+        sim.add_clock(1e-6)
+        with sim.write_vcd("test.vcd"):
+            sim.run()