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axi_adrv9001: Add TDD support
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@ronagyl
ronagyl committed Feb 15, 2021
1 parent 4ae1903 commit 2cbb4f7
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Showing 6 changed files with 421 additions and 10 deletions.
29 changes: 29 additions & 0 deletions library/axi_adrv9001/axi_adrv9001.v
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Original file line number Diff line number Diff line change
Expand Up @@ -38,6 +38,7 @@
module axi_adrv9001 #(
parameter ID = 0,
parameter CMOS_LVDS_N = 0,
parameter TDD_DISABLE = 0,
parameter IO_DELAY_GROUP = "dev_if_delay_group",
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
Expand Down Expand Up @@ -90,6 +91,11 @@ module axi_adrv9001 #(
output tx2_strobe_out_n_NC,
output tx2_strobe_out_p_strobe_out,

output rx1_enable,
output rx2_enable,
output tx1_enable,
output tx2_enable,

input delay_clk,

// user interface
Expand Down Expand Up @@ -147,6 +153,14 @@ module axi_adrv9001 #(
input [15:0] dac_2_data_q0,
input dac_2_dunf,

// TDD interface
input tdd_sync,

input gpio_rx1_enable_in,
input gpio_rx2_enable_in,
input gpio_tx1_enable_in,
input gpio_tx2_enable_in,

// axi interface
input s_axi_aclk,
input s_axi_aresetn,
Expand Down Expand Up @@ -360,6 +374,7 @@ module axi_adrv9001 #(
.NUM_LANES (NUM_LANES),
.CMOS_LVDS_N (CMOS_LVDS_N),
.DRP_WIDTH (DRP_WIDTH),
.TDD_DISABLE (TDD_DISABLE),
.FPGA_TECHNOLOGY (FPGA_TECHNOLOGY),
.FPGA_FAMILY (FPGA_FAMILY),
.SPEED_GRADE (SPEED_GRADE),
Expand Down Expand Up @@ -456,6 +471,15 @@ module axi_adrv9001 #(
.delay_rx2_rst (delay_rx2_rst),
.delay_rx2_locked (delay_rx2_locked),

// TDD interface
.tdd_sync (tdd_sync),
.tdd_rx1_rf_en (tdd_rx1_rf_en),
.tdd_tx1_rf_en (tdd_tx1_rf_en),
.tdd_if1_mode (tdd_if1_mode),
.tdd_rx2_rf_en (tdd_rx2_rf_en),
.tdd_tx2_rf_en (tdd_tx2_rf_en),
.tdd_if2_mode (tdd_if2_mode),

.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
Expand All @@ -482,6 +506,11 @@ module axi_adrv9001 #(
assign dac_2_valid_i0 = dac_2_valid;
assign dac_2_valid_q0 = dac_2_valid;

assign rx1_enable = tdd_if1_mode ? tdd_rx1_rf_en : gpio_rx1_enable_in;
assign rx2_enable = tdd_if2_mode ? tdd_rx2_rf_en : gpio_rx2_enable_in;
assign tx1_enable = tdd_if1_mode ? tdd_tx1_rf_en : gpio_tx1_enable_in;
assign tx2_enable = tdd_if2_mode ? tdd_tx2_rf_en : gpio_tx2_enable_in;

// up bus interface
up_axi #(
.AXI_ADDRESS_WIDTH(15)
Expand Down
121 changes: 112 additions & 9 deletions library/axi_adrv9001/axi_adrv9001_core.v
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Original file line number Diff line number Diff line change
Expand Up @@ -40,6 +40,7 @@ module axi_ad9001_core #(
parameter CMOS_LVDS_N = 0,
parameter NUM_LANES = 3,
parameter DRP_WIDTH = 5,
parameter TDD_DISABLE = 0,
parameter FPGA_TECHNOLOGY = 0,
parameter FPGA_FAMILY = 0,
parameter SPEED_GRADE = 0,
Expand Down Expand Up @@ -140,6 +141,16 @@ module axi_ad9001_core #(
output [DRP_WIDTH*NUM_LANES-1:0] up_rx2_dwdata,
input [DRP_WIDTH*NUM_LANES-1:0] up_rx2_drdata,

// TDD interface
input tdd_sync,

output tdd_rx1_rf_en,
output tdd_tx1_rf_en,
output tdd_if1_mode,
output tdd_rx2_rf_en,
output tdd_tx2_rf_en,
output tdd_if2_mode,

// processor interface

input up_rstn,
Expand All @@ -154,9 +165,9 @@ module axi_ad9001_core #(
output reg up_rack
);

wire up_wack_s[0:5];
wire [31:0] up_rdata_s[0:5];
wire up_rack_s[0:5];
wire [7:0] up_wack_s;
wire [31:0] up_rdata_s[0:7];
wire [7:0] up_rack_s;

wire tx1_data_valid_A;
wire [15:0] tx1_data_i_A;
Expand Down Expand Up @@ -235,9 +246,16 @@ module axi_ad9001_core #(
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_s[0] | up_rdata_s[1] | up_rdata_s[2] | up_rdata_s[3] | up_rdata_s[4] | up_rdata_s[5];
up_rack <= up_rack_s[0] | up_rack_s[1] | up_rack_s[2] | up_rack_s[3] | up_rack_s[4] | up_rack_s[5];
up_wack <= up_wack_s[0] | up_wack_s[1] | up_wack_s[2] | up_wack_s[3] | up_wack_s[4] | up_wack_s[5];
up_rdata <= up_rdata_s[0] |
up_rdata_s[1] |
up_rdata_s[2] |
up_rdata_s[3] |
up_rdata_s[4] |
up_rdata_s[5] |
up_rdata_s[6] |
up_rdata_s[7];
up_rack <= |up_rack_s;
up_wack <= |up_wack_s;
end
end

Expand All @@ -257,11 +275,11 @@ module axi_ad9001_core #(
i_rx1 (
.adc_rst (rx1_rst),
.adc_clk (rx1_clk),
.adc_valid_A (rx1_data_valid),
.adc_valid_A (rx1_data_valid & tdd_rx1_valid),
.adc_data_i_A (rx1_data_i),
.adc_data_q_A (rx1_data_q),

.adc_valid_B (rx2_data_valid),
.adc_valid_B (rx2_data_valid & tdd_rx1_valid),
.adc_data_i_B (rx2_data_i),
.adc_data_q_B (rx2_data_q),

Expand Down Expand Up @@ -316,7 +334,7 @@ module axi_ad9001_core #(
i_rx2 (
.adc_rst (rx2_rst_loc),
.adc_clk (rx2_clk),
.adc_valid_A (rx2_data_valid),
.adc_valid_A (rx2_data_valid & tdd_rx2_valid),
.adc_data_i_A (rx2_data_i),
.adc_data_q_A (rx2_data_q),

Expand Down Expand Up @@ -380,6 +398,7 @@ module axi_ad9001_core #(
.dac_single_lane (tx1_single_lane),
.dac_sdr_ddr_n (tx1_sdr_ddr_n),
.dac_r1_mode (tx1_r1_mode),
.tdd_tx_valid (tdd_tx1_valid),
.dac_sync_in (1'b0),
.dac_sync_out (),
.dac_enable_i0 (dac_1_enable_i0),
Expand Down Expand Up @@ -441,6 +460,7 @@ module axi_ad9001_core #(
.dac_enable_q1 (),
.dac_data_q1 (16'b0),
.dac_dunf (dac_2_dunf),
.tdd_tx_valid (tdd_tx2_valid),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
Expand Down Expand Up @@ -497,5 +517,88 @@ module axi_ad9001_core #(
.up_rdata (up_rdata_s[5]),
.up_rack (up_rack_s[5]));

generate
if (TDD_DISABLE == 0) begin

wire tdd_rx2_rf_en_loc;
wire tdd_tx2_rf_en_loc;
wire tdd_if2_mode_loc;

axi_adrv9001_tdd #(
.BASE_ADDRESS (6'h12)
) i_tdd_1 (
.clk (rx1_clk),
.rst (rx1_rst),
.tdd_rx_vco_en (),
.tdd_tx_vco_en (),
.tdd_rx_rf_en (tdd_rx1_rf_en),
.tdd_tx_rf_en (tdd_tx1_rf_en),
.tdd_enabled (tdd_if1_mode),
.tdd_status (8'h0),
.tdd_sync (tdd_sync),
.tdd_sync_cntr (),
.tdd_tx_valid (tdd_tx1_valid),
.tdd_rx_valid (tdd_rx1_valid),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[6]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[6]),
.up_rack (up_rack_s[6]));

axi_adrv9001_tdd #(
.BASE_ADDRESS (6'h13)
) i_tdd_2 (
.clk (rx2_clk),
.rst (rx2_rst),
.tdd_rx_vco_en (),
.tdd_tx_vco_en (),
.tdd_rx_rf_en (tdd_rx2_rf_en_loc),
.tdd_tx_rf_en (tdd_tx2_rf_en_loc),
.tdd_enabled (tdd_if2_mode_loc),
.tdd_status (8'h0),
.tdd_sync (tdd_sync),
.tdd_sync_cntr (),
.tdd_tx_valid (tdd_tx2_valid),
.tdd_rx_valid (tdd_rx2_valid),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq),
.up_waddr (up_waddr),
.up_wdata (up_wdata),
.up_wack (up_wack_s[7]),
.up_rreq (up_rreq),
.up_raddr (up_raddr),
.up_rdata (up_rdata_s[7]),
.up_rack (up_rack_s[7]));

assign tdd_rx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_rx2_rf_en_loc : tdd_rx1_rf_en;
assign tdd_tx2_rf_en = tx1_r1_mode&rx1_r1_mode ? tdd_tx2_rf_en_loc : tdd_tx1_rf_en;
assign tdd_if2_mode = tx1_r1_mode&rx1_r1_mode ? tdd_if2_mode_loc : tdd_if1_mode;

end else begin
assign up_wack_s[6] = 1'b0;
assign up_rack_s[6] = 1'b0;
assign up_rdata_s[6] = 32'h0;
assign up_wack_s[7] = 1'b0;
assign up_rack_s[7] = 1'b0;
assign up_rdata_s[7] = 32'h0;
assign tdd_rx1_rf_en = 1'b1;
assign tdd_tx1_rf_en = 1'b1;
assign tdd_if1_mode = 1'b0;
assign tdd_tx1_valid = 1'b1;
assign tdd_rx1_valid = 1'b1;
assign tdd_rx2_rf_en = 1'b1;
assign tdd_tx2_rf_en = 1'b1;
assign tdd_if2_mode = 1'b0;
assign tdd_tx2_valid = 1'b1;
assign tdd_rx2_valid = 1'b1;
end
endgenerate

endmodule

15 changes: 15 additions & 0 deletions library/axi_adrv9001/axi_adrv9001_hw.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,9 @@ ad_ip_files axi_adrv9001 [list\
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
"$ad_hdl_dir/library/common/ad_tdd_control.v" \
"$ad_hdl_dir/library/common/ad_addsub.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
"$ad_hdl_dir/library/common/up_clock_mon.v" \
Expand Down Expand Up @@ -46,6 +49,7 @@ ad_ip_files axi_adrv9001 [list\
"axi_adrv9001_tx_channel.v" \
"axi_adrv9001_core.v" \
"axi_adrv9001_constr.sdc" \
"axi_adrv9001_tdd.v" \
"axi_adrv9001.v" ]

# parameters
Expand Down Expand Up @@ -163,6 +167,13 @@ add_interface_port dac_2_ch_1 dac_2_data_q0 data Input 16

ad_interface signal dac_2_dunf input 1 unf

add_interface tdd_if conduit end
add_interface_port tdd_if gpio_rx1_enable_in rx1_enable_in Input 1
add_interface_port tdd_if gpio_rx2_enable_in rx2_enable_in Input 1
add_interface_port tdd_if gpio_tx1_enable_in tx1_enable_in Input 1
add_interface_port tdd_if gpio_tx2_enable_in tx2_enable_in Input 1
add_interface_port tdd_if tdd_sync tdd_sync_in Input 1

# updates

proc axi_adrv9001_elab {} {
Expand Down Expand Up @@ -197,13 +208,15 @@ proc axi_adrv9001_elab {} {
add_interface_port device_if rx1_qdata_in_n_qdata2 rx1_qdata_in_n_qdata2 Input 1
add_interface_port device_if rx1_qdata_in_p_qdata3 rx1_qdata_in_p_qdata3 Input 1
add_interface_port device_if rx1_strobe_in_p_strobe_in rx1_strobe_in_p_strobe_in Input 1
add_interface_port device_if rx1_enable rx1_enable Output 1

add_interface_port device_if rx2_dclk_in_p_dclk_in rx2_dclk_in_p_dclk_in Input 1
add_interface_port device_if rx2_idata_in_n_idata0 rx2_idata_in_n_idata0 Input 1
add_interface_port device_if rx2_idata_in_p_idata1 rx2_idata_in_p_idata1 Input 1
add_interface_port device_if rx2_qdata_in_n_qdata2 rx2_qdata_in_n_qdata2 Input 1
add_interface_port device_if rx2_qdata_in_p_qdata3 rx2_qdata_in_p_qdata3 Input 1
add_interface_port device_if rx2_strobe_in_p_strobe_in rx2_strobe_in_p_strobe_in Input 1
add_interface_port device_if rx2_enable rx2_enable Output 1

add_interface_port device_if tx1_dclk_out_p_dclk_out tx1_dclk_out_p_dclk_out Output 1
add_interface_port device_if tx1_dclk_in_p_dclk_in tx1_dclk_in_p_dclk_in Input 1
Expand All @@ -212,6 +225,7 @@ proc axi_adrv9001_elab {} {
add_interface_port device_if tx1_qdata_out_n_qdata2 tx1_qdata_out_n_qdata2 Output 1
add_interface_port device_if tx1_qdata_out_p_qdata3 tx1_qdata_out_p_qdata3 Output 1
add_interface_port device_if tx1_strobe_out_p_strobe_out tx1_strobe_out_p_strobe_out Output 1
add_interface_port device_if tx1_enable tx1_enable Output 1

add_interface_port device_if tx2_dclk_out_p_dclk_out tx2_dclk_out_p_dclk_out Output 1
add_interface_port device_if tx2_dclk_in_p_dclk_in tx2_dclk_in_p_dclk_in Input 1
Expand All @@ -220,6 +234,7 @@ proc axi_adrv9001_elab {} {
add_interface_port device_if tx2_qdata_out_n_qdata2 tx2_qdata_out_n_qdata2 Output 1
add_interface_port device_if tx2_qdata_out_p_qdata3 tx2_qdata_out_p_qdata3 Output 1
add_interface_port device_if tx2_strobe_out_p_strobe_out tx2_strobe_out_p_strobe_out Output 1
add_interface_port device_if tx2_enable tx2_enable Output 1
}
}

4 changes: 4 additions & 0 deletions library/axi_adrv9001/axi_adrv9001_ip.tcl
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,9 @@ adi_ip_files axi_adrv9001 [list \
"$ad_hdl_dir/library/common/ad_dds_2.v" \
"$ad_hdl_dir/library/common/ad_dds.v" \
"$ad_hdl_dir/library/common/ad_datafmt.v" \
"$ad_hdl_dir/library/common/up_tdd_cntrl.v" \
"$ad_hdl_dir/library/common/ad_tdd_control.v" \
"$ad_hdl_dir/library/common/ad_addsub.v" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \
Expand Down Expand Up @@ -47,6 +50,7 @@ adi_ip_files axi_adrv9001 [list \
"axi_adrv9001_tx_channel.v" \
"axi_adrv9001_core.v" \
"axi_adrv9001_constr.xdc" \
"axi_adrv9001_tdd.v" \
"axi_adrv9001.v" ]

adi_ip_properties axi_adrv9001
Expand Down
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