ArchPPC32 has incorrect Counter register number

[jeffball55]

Similar to issue #27, the Counter register is represented by the a number rather than register name. See below for the IR instructions decoding a "mtctr r0" instruction in big endian PowerPC. Unlike issue #27 though, this is less problematic as the counter register is architecture specific anyway.

>>> pyvex.IRSB('\x7c\x09\x03\xa6', 0x40000, archinfo.arch_from_id('PPC32')).pp()
IRSB {
   t0:Ity_I32 t1:Ity_I32

   00 | IR-NoOp
   01 | IR-NoOp
   02 | IR-NoOp
   03 | IR-NoOp
   04 | IR-NoOp
   05 | IR-NoOp
   06 | IR-NoOp
   07 | IR-NoOp
   08 | IR-NoOp
   09 | IR-NoOp
   10 | IR-NoOp
   11 | IR-NoOp
   12 | IR-NoOp
   13 | IR-NoOp
   14 | IR-NoOp
   15 | ------ IMark(0x40000, 4, 0) ------
   16 | t0 = GET:I32(r0)
   17 | PUT(1176) = t0
   18 | PUT(pc) = 0x00040004
   19 | t1 = GET:I32(pc)
   NEXT: PUT(pc) = t1; Ijk_Boring
}

[rhelmot]

This is now fixed. I wrote a script to do direct parsing of the vex structs, so hopefully issues of this variety are fixed for good.