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Merge 3D maze game #354

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Commits on Mar 4, 2022

  1. Makefile: depend on soc_extra_v

    Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
    mkj committed Mar 4, 2022
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  2. valentyusb: Add USB UART to SOC and OrangeCrab

    An extra uart is added at 0xc0008000 attached to valentyusb, using
    the OrangeCrab's onboard USB port.
    This has a liteuart interface, an identifier bit is added to syscon.
    
    Generated from branch hw_cdc_eptri of
    https://github.com/litex-hub/valentyusb
    
    The generate script is based on valentyusb/sim/generate_verilog.py
    
    UARTUSB: usbserial@8000 {
            device_type = "serial";
            compatible = "litex,liteuart";
            reg = <0x8000 0x100>;
            interrupts = <0x15 0x1>;
    };
    
    (requires extra kernel patches for early console at present v5.16)
    
    Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
    mkj committed Mar 4, 2022
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  3. valentyusb: Add software for liteuart console

    usb_hello is a copy of hello_world but uses both consoles
    
    Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
    mkj committed Mar 4, 2022
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  4. Makefile: Don't force generic USE_LITEDRAM=true

    That makes it easier to override a non-litedram build for testing
    RAM_INIT_FILE, eg
    
    make microwatt.dfu  LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=false  RAM_INIT_FILE=usb_hello/usb_hello.hex
    
    Signed-off-by: Matt Johnston <matt@codeconstruct.com.au>
    mkj committed Mar 4, 2022
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  5. add 3d game

    I added a simple 3D maze game that is a pretty impressive demo of what Microwatt can do.
    
    It's based on antonblanchard#347
    
    Signed-off-by: Jacob Lifshay <programmerjake@gmail.com>
    programmerjake committed Mar 4, 2022
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Commits on Mar 15, 2022

  1. fpu: Make inverse_table a constant

    GHDL synthesis is complaining that inverse_table is never stored to.
    Change it to a constant.
    
    Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
    antonblanchard committed Mar 15, 2022
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  2. xics: Fix warning when comparing two std_ulogic_vectors

    Use unsigned() to make it clear what we are doing.
    
    Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
    antonblanchard committed Mar 15, 2022
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  3. Remove unused sequential signal from Fetch1ToIcacheType

    GHDL synthesis is flagging a warning about this.
    
    Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
    antonblanchard committed Mar 15, 2022
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  4. Merge pull request antonblanchard#357 from antonblanchard/xics-warning

    xics: Fix warning when comparing two std_ulogic_vectors
    mikey committed Mar 15, 2022
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  5. Merge pull request antonblanchard#356 from antonblanchard/fpu-constant

    fpu: Make inverse_table a constant
    mikey committed Mar 15, 2022
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  6. Merge pull request antonblanchard#358 from antonblanchard/unused-sig

    Remove unused sequential signal from Fetch1ToIcacheType
    mikey committed Mar 15, 2022
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Commits on Mar 17, 2022

  1. wishbone_bram_wrapper ram_addr_bits is 1 bit off

    log2ceil() returns the number of bits required to store a value, so we
    need to pass in memory_size-1, not memory_size.
    
    Every other user of log2ceil() gets this right.
    
    Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
    antonblanchard committed Mar 17, 2022
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Commits on Mar 18, 2022

  1. Merge pull request antonblanchard#360 from antonblanchard/log2ceil-issue

    wishbone_bram_wrapper ram_addr_bits is 1 bit off
    mikey committed Mar 18, 2022
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Commits on Mar 21, 2022

  1. Allow ALT_RESET_ADDRESS to be overridden

    This allows us to boot from flash for example.
    
    Signed-off-by: Anton Blanchard <anton@linux.ibm.com>
    antonblanchard committed Mar 21, 2022
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Commits on Mar 22, 2022

  1. Merge pull request antonblanchard#361 from antonblanchard/alt-reset-a…

    …ddress
    
    Allow ALT_RESET_ADDRESS to be overridden
    mikey committed Mar 22, 2022
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  2. Merge remote-tracking branch 'to-be-merged/merge-3d-game'

    Tobias Platen committed Mar 22, 2022
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