[VTA] Timing closure fix #1489
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[VTA] Timing closure fix #1489
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tqchen
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sergei-mironov
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tqchen
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This change is a one-liner (or shall I say a one-characterer)
Refers to this issue: https://discuss.tvm.ai/t/timing-violation-for-vta-hardware-implementation/508/5
Lowered clock period target for more aggressive pipelining and close timing for default config.
No noticeable degradation on performance, e2e resnet-18 inference still at 0.4s.