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Verify register kinds and regions in BIR #995
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What does this mean? It's the graph formed by the forward edges that is acyclic. |
Reached from where? Must be reachable via forward edges only. |
Point is that backward branch must point to a block that is the entry of a loop. |
Really? I don't think so. How are you going to find every single-entry/single-exit region. |
Can't we determine the location of single-entry/single-exit regions with conditional branch instructions? |
When the graph created by edges in the function code diverges into a different path and eventually rejoin, such a branching is considered a region to be used for WASM. |
@ushirask Does it mean that every conditional branch is the entry point of a single-entry, single-exit region? Or does it mean every place that is a join has to be the exit point of a region? Or something else? |
We had a chat yesterday and concluded, yes, every conditional should be a region entry, but exit should only appear when all the paths that diverged at the entry are merged. Given that Ballerina is a structured language that may mean every merge, but Ushira need to find out how the Definition is not finalized since we found some complicated cases where it was not clear to us how the regions should be created. import ballerina/io;
public function main() {
int i = 6;
while i < 10 {
io:println(i);
if i == 8 {
break;
}
i += 1;
}
io:println(true);
}
Current algorithm gives: [{"entry":1,"exit":3,"parent":null,"kind":"REGION_LOOP"},{"entry":2,"exit":5,"parent":0,"kind":"REGION_COND"}] We'll have another chat with Poorna to see if this is what is expected. |
Sounds plausible.
Otherwise it wouldn't be single exit, right? |
Correct. |
We had a long chat today. We came to some rough conclusions. After some reflection, I have simplified them as follows.
[1] Latter half of the 2nd requirement (following "unless") is not currently implemented. As far as I can see, it doesn't affect the correctness of the wback. But I think we should fix it. |
Though about the above "unless ..." part. But It's only complicated because I am explaining how it should appear in the BIR. If we think about Ballerina code, it's an So I think generating it will be trivial🤞. Verification may take a bit of work. It is correct even without "unless ..." part. But since it's trivial to generate and harder to recover in the backend, I suggest we'll include that as a part of the definition. |
In the given graph according to the above definition the loop region starting from bb1 would be 1 to 3. However the region currently created in the frontend is from 1 to 4, which also seems to be allowed by WASM. We can either,
|
LLVM's loop definition has multiple exit blocks https://llvm.org/docs/LoopTerminology.html#terminology |
|
Tmp registers should only be used within the block it was initialized, but this is not currently correct in the front end and should be fixed. |
Description:
Verify register kinds and regions in the BIR verfier
Check if
Temp registers are assigned once and only once as a result of an instruction.
List/map operand in ListSetInsn / MappingSetInsn is not a final register.
Temp registered are assigned in a previous instruction in the block before being used as a operand in another instruction.
Narrow register is a subtype of underlying unnarrowed register.
Verify regions
Check if
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