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In my case, the instruction is ldr.w r1, [pc, #-80], the opcode is f85f 1050,
generated ldr R1, [R1, R0], but shoule be ldr R1, [R1].
But for ldr.w r1, [pc, #936], opcode is f8df 13a8, the generated instruction is correct.
Since it's an old issue and I have no way of testing it at the moment, I'm going to close it in the effort to clean up the repo. If anyone still requires this fix, please re-open the issue and I can look into it.
if
imm12 < 0x40
,the instruction generated by
thumb_load_store_single_reg_imm12_32
isldr Rt, [Rn, Rm, LSL imm]
,rather than
ldr Rt, [Rn, imm]
such as
if we want to generate
ldr R1, [R1]
,but actually
ldr R1, [R1, R0]
generated.The text was updated successfully, but these errors were encountered: