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Removing Timer Usage Flags #12862

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merged 1 commit into from Jun 6, 2023
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Removing Timer Usage Flags #12862

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112 changes: 56 additions & 56 deletions src/main/drivers/at32/timer_at32f43x.c
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Expand Up @@ -52,71 +52,71 @@ const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
#if defined(USE_TIMER_MGMT)
const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
// Port A
DEF_TIM(TMR2, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH1, PA0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH2, PA1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH3, PA2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH4, PA3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PA6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH2, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PA7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1, PA8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH2, PA9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3, PA10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH4, PA11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA0, 0, 0, 0),
DEF_TIM(TMR2, CH2, PA1, 0, 0, 0),
DEF_TIM(TMR2, CH3, PA2, 0, 0, 0),
DEF_TIM(TMR2, CH4, PA3, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA5, 0, 0, 0),
DEF_TIM(TMR2, CH1, PA15, 0, 0, 0),
DEF_TIM(TMR5, CH1, PA0, 0, 0, 0),
DEF_TIM(TMR5, CH2, PA1, 0, 0, 0),
DEF_TIM(TMR5, CH3, PA2, 0, 0, 0),
DEF_TIM(TMR5, CH4, PA3, 0, 0, 0),
DEF_TIM(TMR3, CH1, PA6, 0, 0, 0),
DEF_TIM(TMR3, CH2, PA7, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA5, 0, 0, 0),
DEF_TIM(TMR8, CH1N, PA7, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PA7, 0, 0, 0),
DEF_TIM(TMR1, CH1, PA8, 0, 0, 0),
DEF_TIM(TMR1, CH2, PA9, 0, 0, 0),
DEF_TIM(TMR1, CH3, PA10, 0, 0, 0),
DEF_TIM(TMR1, CH4, PA11, 0, 0, 0),

// Port B ORDER BY MUX 1 2 3
//MUX1
DEF_TIM(TMR1, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB3, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH1, PB8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH3, PB10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PB13, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR1, CH2N, PB0, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB1, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB2, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB3, 0, 0, 0),
DEF_TIM(TMR2, CH1, PB8, 0, 0, 0),
DEF_TIM(TMR2, CH2, PB9, 0, 0, 0),
DEF_TIM(TMR2, CH3, PB10, 0, 0, 0),
DEF_TIM(TMR2, CH4, PB11, 0, 0, 0),
DEF_TIM(TMR1, CH1N, PB13, 0, 0, 0),
DEF_TIM(TMR1, CH2N, PB14, 0, 0, 0),
DEF_TIM(TMR1, CH3N, PB15, 0, 0, 0),
//MUX2
DEF_TIM(TMR3, CH3, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH4, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR20, CH1, PB2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PB4, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH2, PB5, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR4, CH1, PB6, TIM_USE_ANY, 0, 13, 9),
DEF_TIM(TMR4, CH2, PB7, TIM_USE_ANY, 0, 12, 9),
DEF_TIM(TMR4, CH3, PB8, TIM_USE_ANY, 0, 11, 9),
DEF_TIM(TMR4, CH4, PB9, TIM_USE_ANY, 0, 10, 9),
DEF_TIM(TMR5, CH4, PB11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH1, PB12, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH3, PB0, 0, 0, 0),
DEF_TIM(TMR3, CH4, PB1, 0, 0, 0),
DEF_TIM(TMR20, CH1, PB2, 0, 0, 0),
DEF_TIM(TMR3, CH1, PB4, 0, 0, 0),
DEF_TIM(TMR3, CH2, PB5, 0, 0, 0),
DEF_TIM(TMR4, CH1, PB6, 0, 13, 9),
DEF_TIM(TMR4, CH2, PB7, 0, 12, 9),
DEF_TIM(TMR4, CH3, PB8, 0, 11, 9),
DEF_TIM(TMR4, CH4, PB9, 0, 10, 9),
DEF_TIM(TMR5, CH4, PB11, 0, 0, 0),
DEF_TIM(TMR5, CH1, PB12, 0, 0, 0),
//MUX3
DEF_TIM(TMR8, CH2N, PB0, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB1, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2N, PB14, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB15, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2N, PB0, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB1, 0, 0, 0),
DEF_TIM(TMR8, CH2N, PB14, 0, 0, 0),
DEF_TIM(TMR8, CH3N, PB15, 0, 0, 0),

// Port C ORDER BY MUX 1 2 3
//MUX2
DEF_TIM(TMR20, CH2, PC2, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR3, CH1, PC6, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH2, PC7, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH3, PC8, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR3, CH4, PC9, TIM_USE_ANY, 0, 0, 12),
DEF_TIM(TMR5, CH2, PC10, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR5, CH3, PC11, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR20, CH2, PC2, 0, 0, 0),
DEF_TIM(TMR3, CH1, PC6, 0, 0, 12),
DEF_TIM(TMR3, CH2, PC7, 0, 0, 12),
DEF_TIM(TMR3, CH3, PC8, 0, 0, 12),
DEF_TIM(TMR3, CH4, PC9, 0, 0, 12),
DEF_TIM(TMR5, CH2, PC10, 0, 0, 0),
DEF_TIM(TMR5, CH3, PC11, 0, 0, 0),
//MUX 3
DEF_TIM(TMR8, CH1, PC6, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH2, PC7, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH3, PC8, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH4, PC9, TIM_USE_ANY, 0, 0, 0),
DEF_TIM(TMR8, CH1, PC6, 0, 0, 0),
DEF_TIM(TMR8, CH2, PC7, 0, 0, 0),
DEF_TIM(TMR8, CH3, PC8, 0, 0, 0),
DEF_TIM(TMR8, CH4, PC9, 0, 0, 0),
};
#endif

Expand Down
3 changes: 1 addition & 2 deletions src/main/drivers/at32/timer_def.h
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Expand Up @@ -138,11 +138,10 @@
@dmaopt dma channel index used for timer channel data transmit
@upopt USE_DSHOT_DMAR timeup dma channel index
*/
#define DEF_TIM(tim, chan, pin, flags, out, dmaopt, upopt) { \
#define DEF_TIM(tim, chan, pin, out, dmaopt, upopt) { \
tim, \
TIMER_GET_IO_TAG(pin), \
DEF_TIM_CHANNEL(CH_ ## chan), \
flags, \
(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
DEF_TIM_DMA_COND(/* add comma */ , \
Expand Down
34 changes: 17 additions & 17 deletions src/main/drivers/stm32/dshot_bitbang.c
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Expand Up @@ -101,16 +101,16 @@ FAST_DATA_ZERO_INIT timeUs_t dshotFrameUs;
const timerHardware_t bbTimerHardware[] = {
#if defined(STM32F4) || defined(STM32F7)
#if !defined(STM32F411xE)
DEF_TIM(TIM8, CH1, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM8, CH2, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM8, CH3, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM8, CH4, NONE, TIM_USE_NONE, 0, 0),
DEF_TIM(TIM8, CH1, NONE, 0, 1),
DEF_TIM(TIM8, CH2, NONE, 0, 1),
DEF_TIM(TIM8, CH3, NONE, 0, 1),
DEF_TIM(TIM8, CH4, NONE, 0, 0),
#endif
DEF_TIM(TIM1, CH1, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM1, CH1, NONE, TIM_USE_NONE, 0, 2),
DEF_TIM(TIM1, CH2, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM1, CH3, NONE, TIM_USE_NONE, 0, 1),
DEF_TIM(TIM1, CH4, NONE, TIM_USE_NONE, 0, 0),
DEF_TIM(TIM1, CH1, NONE, 0, 1),
DEF_TIM(TIM1, CH1, NONE, 0, 2),
DEF_TIM(TIM1, CH2, NONE, 0, 1),
DEF_TIM(TIM1, CH3, NONE, 0, 1),
DEF_TIM(TIM1, CH4, NONE, 0, 0),

#elif defined(STM32G4) || defined(STM32H7)
// XXX TODO: STM32G4 and STM32H7 can use any timer for pacing
Expand All @@ -121,14 +121,14 @@ const timerHardware_t bbTimerHardware[] = {
// 4 motors scattered across 4 different GPIO ports.
// - For hexas (and larger), more channels may become necessary,
// in which case the DMA request numbers should be modified.
DEF_TIM(TIM8, CH1, NONE, TIM_USE_NONE, 0, 0, 0),
DEF_TIM(TIM8, CH2, NONE, TIM_USE_NONE, 0, 1, 0),
DEF_TIM(TIM8, CH3, NONE, TIM_USE_NONE, 0, 2, 0),
DEF_TIM(TIM8, CH4, NONE, TIM_USE_NONE, 0, 3, 0),
DEF_TIM(TIM1, CH1, NONE, TIM_USE_NONE, 0, 0, 0),
DEF_TIM(TIM1, CH2, NONE, TIM_USE_NONE, 0, 1, 0),
DEF_TIM(TIM1, CH3, NONE, TIM_USE_NONE, 0, 2, 0),
DEF_TIM(TIM1, CH4, NONE, TIM_USE_NONE, 0, 3, 0),
DEF_TIM(TIM8, CH1, NONE, 0, 0, 0),
DEF_TIM(TIM8, CH2, NONE, 0, 1, 0),
DEF_TIM(TIM8, CH3, NONE, 0, 2, 0),
DEF_TIM(TIM8, CH4, NONE, 0, 3, 0),
DEF_TIM(TIM1, CH1, NONE, 0, 0, 0),
DEF_TIM(TIM1, CH2, NONE, 0, 1, 0),
DEF_TIM(TIM1, CH3, NONE, 0, 2, 0),
DEF_TIM(TIM1, CH4, NONE, 0, 3, 0),

#else
#error MCU dependent code required
Expand Down
12 changes: 4 additions & 8 deletions src/main/drivers/stm32/timer_def.h
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Expand Up @@ -145,11 +145,10 @@

#if defined(STM32F4)

#define DEF_TIM(tim, chan, pin, flags, out, dmaopt) { \
#define DEF_TIM(tim, chan, pin, out, dmaopt) { \
tim, \
TIMER_GET_IO_TAG(pin), \
DEF_TIM_CHANNEL(CH_ ## chan), \
flags, \
(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
DEF_TIM_AF(TIM_ ## tim) \
DEF_TIM_DMA_COND(/* add comma */ , \
Expand Down Expand Up @@ -250,11 +249,10 @@
#define DEF_TIM_DMA__BTCH_TIM14_UP NONE

#elif defined(STM32F7)
#define DEF_TIM(tim, chan, pin, flags, out, dmaopt) { \
#define DEF_TIM(tim, chan, pin, out, dmaopt) { \
tim, \
TIMER_GET_IO_TAG(pin), \
DEF_TIM_CHANNEL(CH_ ## chan), \
flags, \
(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
DEF_TIM_DMA_COND(/* add comma */ , \
Expand Down Expand Up @@ -476,11 +474,10 @@
#define DEF_TIM_AF__PI7__TCH_TIM8_CH3 D(3, 8)

#elif defined(STM32H7)
#define DEF_TIM(tim, chan, pin, flags, out, dmaopt, upopt) { \
#define DEF_TIM(tim, chan, pin, out, dmaopt, upopt) { \
tim, \
TIMER_GET_IO_TAG(pin), \
DEF_TIM_CHANNEL(CH_ ## chan), \
flags, \
(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
DEF_TIM_DMA_COND(/* add comma */ , \
Expand Down Expand Up @@ -829,11 +826,10 @@
// Missing from FW1.0.0 library?
#define GPIO_AF12_TIM1 ((uint8_t)0x0B) /* TIM1 Alternate Function mapping */

#define DEF_TIM(tim, chan, pin, flags, out, dmaopt, upopt) { \
#define DEF_TIM(tim, chan, pin, out, dmaopt, upopt) { \
tim, \
TIMER_GET_IO_TAG(pin), \
DEF_TIM_CHANNEL(CH_ ## chan), \
flags, \
(DEF_TIM_OUTPUT(CH_ ## chan) | out), \
DEF_TIM_AF(TCH_## tim ## _ ## chan, pin) \
DEF_TIM_DMA_COND(/* add comma */ , \
Expand Down
3 changes: 0 additions & 3 deletions src/main/drivers/stm32/timer_hal.c
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Expand Up @@ -1031,9 +1031,6 @@ void timerInit(void)
#if defined(STM32F4) || defined(STM32F7) || defined(STM32H7)
for (unsigned timerIndex = 0; timerIndex < TIMER_CHANNEL_COUNT; timerIndex++) {
const timerHardware_t *timerHardwarePtr = &TIMER_HARDWARE[timerIndex];
if (timerHardwarePtr->usageFlags == TIM_USE_NONE) {
continue;
}
// XXX IOConfigGPIOAF in timerInit should eventually go away.
IOConfigGPIOAF(IOGetByTag(timerHardwarePtr->tag), IOCFG_AF_PP, timerHardwarePtr->alternateFunction);
}
Expand Down