fstr_project - a simple clock divider in two languages

Example project for APIO that has initial support for both VHDL and Verilog toolchains

It includes example code in VHDL and Verilog and a common SConstruct file.

Test benches and a top level for the ice40 (TinyFPGA BX) included as well.

For VHDL usage, first source the env.sh script.