Pipelining not optimal

[jonwoodruff]

Instructions very rarely commit back-to-back in the pipeline.
This is an example trace with the first number being time:
31710 instret:456 PC:0x800005b8 instr:0x02000e93 iType:Alu [doCommitNormalInst [0]]
31710 instret:457 PC:0x800005bc instr:0x02400193 iType:Alu [doCommitNormalInst [1]]
31730 instret:458 PC:0x800005c0 instr:0x03d11863 iType:Br [doCommitNormalInst [0]]
31730 instret:459 PC:0x800005c4 instr:0x000000b3 iType:Alu [doCommitNormalInst [1]]
31750 instret:460 PC:0x800005c8 instr:0x00000e93 iType:Alu [doCommitNormalInst [0]]
31750 instret:461 PC:0x800005cc instr:0x02500193 iType:Alu [doCommitNormalInst [1]]
31770 instret:462 PC:0x800005d0 instr:0x03d09063 iType:Br [doCommitNormalInst [0]]
31770 instret:463 PC:0x800005d4 instr:0x01000093 iType:Alu [doCommitNormalInst [1]]

While the pipe is super-scalar, it's clearly not committing instructions optimally.
This appears to have been introduced between commit:
9683df0
and commit
f369ed1
I'll bisect a little more.

[jrtc27]

This should be resolved now #2 has been merged.