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Reduce MT and MR TWI acks to 0 cycles #455

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Reduce MT and MR TWI acks to 0 cycles #455

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4 changes: 2 additions & 2 deletions simavr/sim/avr_twi.c
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Original file line number Diff line number Diff line change
Expand Up @@ -319,7 +319,7 @@ avr_twi_write(

if (p->peer_addr & 1) { // read ?
p->state |= TWI_COND_READ; // always allow read to start with
_avr_twi_delay_state(p, 9,
_avr_twi_delay_state(p, 0,
p->state & TWI_COND_ACK ?
TWI_MRX_ADR_ACK : TWI_MRX_ADR_NACK);
} else {
Expand All @@ -328,7 +328,7 @@ avr_twi_write(
p->state & TWI_COND_ACK ?
TWI_MTX_ADR_ACK : TWI_MTX_ADR_NACK);
}else{
_avr_twi_delay_state(p, 9,
_avr_twi_delay_state(p, 0,
p->state & TWI_COND_ACK ?
TWI_MTX_DATA_ACK : TWI_MTX_DATA_NACK);
}
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