Create pins and wires during port and cable addition in definition

[ganeshgore]

Added optional pins and wires parameters in create_port and create_cable methods of definition.
It will create a defined number of pins or wires while creating a Port or cable.

• Do not break existing functionality
• Unit tests are updated

[ganeshgore]

Parameter sequence keeps changing arbitrary during comparison in the following test

spydrnet/spydrnet/composers/verilog/tests/test_composer_unit.py

Line 550 in 7ab6d6e

assert composer.file.compare(expected)

Possibly VERILOG.Parameters should be defined as an OrderedDictionaty or sort parameters during writing.

Travis output

The composer wrote:
"module test_definition
#(
    parameter no_default,
    parameter key = value
)(
    my_port,
    my_port2
);
"
This was compared to:
"module test_definition
#(
    parameter key = value,
    parameter no_default
)(
    my_port,
    my_port2
);
"

[jacobdbrown4]

These additions seem good!

[jacobdbrown4]

Those optional parameter additions look good to me.

Yes I think the OrderedDict() will help that. If you are able to change that and then commit it, I'll merge this PR.