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Merge branch 'develop'
2 parents 4171863 + c5b09b4 commit a05842b

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3 files changed

+17
-16
lines changed

3 files changed

+17
-16
lines changed

cachesimulator/simulator.py

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -7,9 +7,6 @@
77
from cachesimulator.table import Table
88

99

10-
# The character-width of all displayed tables
11-
# Attempt to fit table to size of terminal window, otherwise use default of 80
12-
TABLE_WIDTH = shutil.get_terminal_size((80, 20)).columns
1310
# The names of all reference table columns
1411
REF_COL_NAMES = ('WordAddr', 'BinAddr', 'Tag', 'Index', 'Offset', 'Hit/Miss')
1512
# The minimum number of bits required per group in a prettified binary string
@@ -225,10 +222,10 @@ def read_refs_into_cache(num_sets, num_blocks_per_set, num_index_bits,
225222

226223

227224
# Displays details for each address reference, including its hit/miss status
228-
def display_addr_refs(refs, ref_statuses):
225+
def display_addr_refs(refs, ref_statuses, table_width):
229226

230227
table = Table(
231-
num_cols=len(REF_COL_NAMES), width=TABLE_WIDTH, alignment='right')
228+
num_cols=len(REF_COL_NAMES), width=table_width, alignment='right')
232229
table.header[:] = REF_COL_NAMES
233230

234231
for ref, ref_status in zip(refs, ref_statuses):
@@ -261,10 +258,10 @@ def display_addr_refs(refs, ref_statuses):
261258

262259

263260
# Displays the contents of the given cache as nicely-formatted table
264-
def display_cache(cache):
261+
def display_cache(cache, table_width):
265262

266263
table = Table(
267-
num_cols=len(cache), width=TABLE_WIDTH, alignment='center')
264+
num_cols=len(cache), width=table_width, alignment='center')
268265
table.title = 'Cache'
269266

270267
cache_set_names = sorted(cache.keys())
@@ -306,10 +303,14 @@ def run_simulation(num_blocks_per_set, num_words_per_block, cache_size,
306303
num_sets, num_blocks_per_set, num_index_bits,
307304
num_words_per_block, replacement_policy, refs)
308305

306+
# The character-width of all displayed tables
307+
# Attempt to fit table to terminal width, otherwise use default of 80
308+
table_width = shutil.get_terminal_size((80, 20)).columns
309+
309310
print()
310-
display_addr_refs(refs, ref_statuses)
311+
display_addr_refs(refs, ref_statuses, table_width)
311312
print()
312-
display_cache(cache)
313+
display_cache(cache, table_width)
313314
print()
314315

315316

setup.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ def get_long_description():
1616

1717
setup(
1818
name='cache-simulator',
19-
version='1.0.0',
19+
version='1.0.1',
2020
description='A processor cache simulator for the MIPS ISA',
2121
long_description=get_long_description(),
2222
url='https://github.com/caleb531/cache-simulator',

tests/test_simulator_display.py

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ def test_display_addr_refs():
1818
ref_statuses = ['miss', 'miss', 'HIT', 'miss']
1919
out = io.StringIO()
2020
with contextlib.redirect_stdout(out):
21-
sim.display_addr_refs(refs, ref_statuses)
21+
sim.display_addr_refs(refs, ref_statuses, table_width=TABLE_WIDTH)
2222
table_output = out.getvalue()
2323
num_cols = 6
2424
col_width = TABLE_WIDTH // num_cols
@@ -43,7 +43,7 @@ def test_display_addr_refs_no_tag():
4343
ref_statuses = ['miss', 'miss', 'miss', 'miss']
4444
out = io.StringIO()
4545
with contextlib.redirect_stdout(out):
46-
sim.display_addr_refs(refs, ref_statuses)
46+
sim.display_addr_refs(refs, ref_statuses, table_width=TABLE_WIDTH)
4747
table_output = out.getvalue()
4848
nose.assert_regexp_matches(
4949
table_output, r'\s*{}\s*{}\s*{}'.format(
@@ -58,7 +58,7 @@ def test_display_addr_refs_no_index():
5858
ref_statuses = ['miss', 'miss', 'miss', 'miss']
5959
out = io.StringIO()
6060
with contextlib.redirect_stdout(out):
61-
sim.display_addr_refs(refs, ref_statuses)
61+
sim.display_addr_refs(refs, ref_statuses, table_width=TABLE_WIDTH)
6262
table_output = out.getvalue()
6363
nose.assert_regexp_matches(
6464
table_output, r'\s*{}\s*{}\s*{}'.format(
@@ -73,7 +73,7 @@ def test_display_addr_refs_no_offset():
7373
ref_statuses = ['miss'] * 12
7474
out = io.StringIO()
7575
with contextlib.redirect_stdout(out):
76-
sim.display_addr_refs(refs, ref_statuses)
76+
sim.display_addr_refs(refs, ref_statuses, table_width=TABLE_WIDTH)
7777
table_output = out.getvalue()
7878
nose.assert_regexp_matches(
7979
table_output, r'\s*{}\s*{}\s*{}'.format(
@@ -92,7 +92,7 @@ def test_display_cache():
9292
{'tag': '0000', 'data': [2, 3]},
9393
{'tag': '0010', 'data': [42, 43]},
9494
]
95-
})
95+
}, table_width=TABLE_WIDTH)
9696
table_output = out.getvalue()
9797
num_cols = 2
9898
col_width = TABLE_WIDTH // num_cols
@@ -121,7 +121,7 @@ def test_display_cache_fully_assoc():
121121
{'tag': '0000001', 'data': [2, 3]},
122122
{'tag': '1111110', 'data': [252, 253]}
123123
]
124-
})
124+
}, table_width=TABLE_WIDTH)
125125
table_output = out.getvalue()
126126
nose.assert_regexp_matches(
127127
table_output, '{}\n{}'.format(

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