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Merged PR 136182: Fix ICCM ECC error not reported
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* Fix the GH issue #295, which describes a scenario where ECC errors on reads from ICCM may not trigger the error signal and cause cptra_error_fatal to assert.
* Fix a minor UVM issue in uvmf_soc_ifc that causes intermittent errors during nightly regression.

Related work items: #597603, #597604, #597607
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@calebofearth
calebofearth committed Dec 1, 2023
1 parent c5884b8 commit 15acd7b
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Showing 8 changed files with 377 additions and 96 deletions.
73 changes: 73 additions & 0 deletions src/integration/tb/caliptra_top_tb.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -165,6 +165,8 @@ module caliptra_top_tb (
logic cptra_error_fatal_dly_p;
logic cptra_error_non_fatal_dly_p;

logic rv_dma_resp_error;

logic mbox_apb_dataout_read_ooo;
logic mbox_ooo_read_done;
logic mbox_apb_dataout_read_no_lock;
Expand Down Expand Up @@ -232,7 +234,15 @@ module caliptra_top_tb (
end

else if (ras_test_ctrl.reset_generic_input_wires) begin
`ifdef VERILATOR
generic_input_wires <= {32'h72746C76, ERROR_NONE_SET}; /* 32'h72746c76 is the big-endian ASCII representation of 'vltr' (r t l v) */
`else
generic_input_wires <= {32'h0, ERROR_NONE_SET};
`endif
end

else if (c_state_apb == S_APB_WAIT_ERROR_AXS && rv_dma_resp_error) begin
generic_input_wires <= {32'h0, DMA_ERROR_OBSERVED};
end

else if (c_state_apb == S_APB_RD_HW_ERROR_FATAL && apb_xfer_end) begin
Expand Down Expand Up @@ -1234,6 +1244,69 @@ caliptra_top_tb_services #(

);

`define RV_INST caliptra_top_dut.rvtop
`define RV_IDMA_RESP_INST caliptra_top_dut.responder_inst[`CALIPTRA_SLAVE_SEL_IDMA]
`define RV_DDMA_RESP_INST caliptra_top_dut.responder_inst[`CALIPTRA_SLAVE_SEL_DDMA]
task force_ahb_dma_read(input logic [31:0] address);
while(`RV_INST.dma_hsel) @(posedge core_clk);
force `RV_IDMA_RESP_INST.hreadyout = 1'b0;
force `RV_DDMA_RESP_INST.hreadyout = 1'b0;

force `RV_INST.dma_haddr = address;
force `RV_INST.dma_hsize = 3'b010; // 4-bytes
force `RV_INST.dma_hwrite = 1'b0;
force `RV_INST.dma_hwdata = '0;
force `RV_INST.dma_hreadyin = 1'b1;
force `RV_INST.dma_hsel = 1'b1;
force `RV_INST.dma_htrans = 2'b10;

// Wait for command to be accepted
do @(posedge core_clk); while(!`RV_INST.dma_hreadyout);
force `RV_INST.dma_htrans = 2'b00;
// Wait for response to be provided
do @(posedge core_clk); while(!`RV_INST.dma_hreadyout);
$display("[%t] AHB DMA FORCE READ: Address 0x%x Data 0x%x Resp 0x%x", $time, address, `RV_INST.dma_hrdata, `RV_INST.dma_hresp);
if (`RV_INST.dma_hresp)
rv_dma_resp_error = 1'b1;
release `RV_IDMA_RESP_INST.hreadyout;
release `RV_DDMA_RESP_INST.hreadyout;

release `RV_INST.dma_htrans;
release `RV_INST.dma_haddr;
release `RV_INST.dma_hsize;
release `RV_INST.dma_hwrite;
release `RV_INST.dma_hwdata;
release `RV_INST.dma_hsel;
release `RV_INST.dma_hreadyin;
endtask

task force_ahb_dma_loop_read(input logic [31:0] start_addr, input logic [19:0] count);
automatic logic [31:0] addr;
addr = start_addr;
$display("[%t] AHB DMA FORCE LOOP READ: Start Address 0x%x Count 0x%x", $time, addr, count);
if ($isunknown(start_addr) || $isunknown(addr))
$error("[%t] Unknown signal found: start_addr 0x%x addr 0x%x", $time, start_addr, addr);
repeat(count) begin
force_ahb_dma_read(addr);
addr += 4;
end
endtask

initial begin
fork
forever @(posedge core_clk) begin
if (ras_test_ctrl.dccm_read_burst.start)
force_ahb_dma_loop_read(ras_test_ctrl.dccm_read_burst.addr, ras_test_ctrl.dccm_read_burst.count);
if (ras_test_ctrl.iccm_read_burst.start)
force_ahb_dma_loop_read(ras_test_ctrl.iccm_read_burst.addr, ras_test_ctrl.iccm_read_burst.count);
end
forever @(posedge core_clk) begin
if (c_state_apb != S_APB_WAIT_ERROR_AXS)
rv_dma_resp_error = 1'b0;
end
join
end

caliptra_top_sva sva();

endmodule
8 changes: 8 additions & 0 deletions src/integration/tb/caliptra_top_tb_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -58,6 +58,13 @@ typedef struct packed {
} veer_sram_error_injection_mode_t;

typedef struct packed {
logic [31:0] addr;
logic [19:0] count;
logic start;
} rv_ccm_read_burst_pkt;
typedef struct packed {
rv_ccm_read_burst_pkt dccm_read_burst;
rv_ccm_read_burst_pkt iccm_read_burst;
logic error_injection_seen;
logic reset_generic_input_wires;
logic do_no_lock_access;
Expand All @@ -73,6 +80,7 @@ localparam PROT_OOO_NON_FATAL_OBSERVED = 32'h600dcafe;
localparam ICCM_FATAL_OBSERVED = 32'hdeadaca1;
localparam DCCM_FATAL_OBSERVED = 32'hdeadbeef;
localparam NMI_FATAL_OBSERVED = 32'hdeadc0a7;
localparam DMA_ERROR_OBSERVED = 32'hfadebadd;
localparam ERROR_NONE_SET = 32'hba5eba11; /* default value for a test with no activity observed by TB */

endpackage
37 changes: 37 additions & 0 deletions src/integration/tb/caliptra_top_tb_services.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -240,6 +240,8 @@ module caliptra_top_tb_services
// 8'h9a - Inject invalid zero sign_s into ECC
// 8'ha0: 8'ha7 - Inject HMAC_KEY to kv_key register
// 8'hc0: 8'hc7 - Inject SHA_BLOCK to kv_key register
// 8'hde - ICCM SRAM force loop read (requires read params written to other bytes of generic wires)
// 8'hdf - DCCM SRAM force loop read (requires read params written to other bytes of generic wires)
// 8'he0 - Set random ICCM SRAM single bit error injection
// 8'he1 - Set random ICCM SRAM double bit error injection
// 8'he2 - Set random DCCM SRAM single bit error injection
Expand Down Expand Up @@ -339,6 +341,41 @@ module caliptra_top_tb_services
end
end

always @(negedge clk or negedge cptra_rst_b) begin
if (!cptra_rst_b) begin
ras_test_ctrl.iccm_read_burst.start <= 1'b0;
ras_test_ctrl.iccm_read_burst.count <= '0;
ras_test_ctrl.iccm_read_burst.addr <= '0;
ras_test_ctrl.dccm_read_burst.start <= 1'b0;
ras_test_ctrl.dccm_read_burst.count <= '0;
ras_test_ctrl.dccm_read_burst.addr <= '0;
end
else if((WriteData[7:0] == 8'hde) && mailbox_write) begin
ras_test_ctrl.iccm_read_burst.start <= 1'b1;
ras_test_ctrl.iccm_read_burst.count <= WriteData[31:12];
ras_test_ctrl.iccm_read_burst.addr <= caliptra_top_dut.soc_ifc_top1.i_soc_ifc_reg.field_storage.CPTRA_GENERIC_OUTPUT_WIRES[1].generic_wires.value;
ras_test_ctrl.dccm_read_burst.start <= 1'b0;
ras_test_ctrl.dccm_read_burst.count <= '0;
ras_test_ctrl.dccm_read_burst.addr <= '0;
end
else if((WriteData[7:0] == 8'hdf) && mailbox_write) begin
ras_test_ctrl.iccm_read_burst.start <= 1'b0;
ras_test_ctrl.iccm_read_burst.count <= '0;
ras_test_ctrl.iccm_read_burst.addr <= '0;
ras_test_ctrl.dccm_read_burst.start <= 1'b1;
ras_test_ctrl.dccm_read_burst.count <= WriteData[31:12];
ras_test_ctrl.dccm_read_burst.addr <= caliptra_top_dut.soc_ifc_top1.i_soc_ifc_reg.field_storage.CPTRA_GENERIC_OUTPUT_WIRES[1].generic_wires.value;
end
else begin
ras_test_ctrl.iccm_read_burst.start <= 1'b0;
ras_test_ctrl.iccm_read_burst.count <= '0;
ras_test_ctrl.iccm_read_burst.addr <= '0;
ras_test_ctrl.dccm_read_burst.start <= 1'b0;
ras_test_ctrl.dccm_read_burst.count <= '0;
ras_test_ctrl.dccm_read_burst.addr <= '0;
end
end

initial ras_test_ctrl.error_injection_seen = 1'b0;
always @(negedge clk) begin
if (mailbox_write && WriteData[7:0] == 8'hfd) begin
Expand Down

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