Aggregate literals now materialize const wires (#3515)

chipsalliance · Aug 30, 2023 · 9a64ac3 · 9a64ac3
1 parent 2cf97e2
commit 9a64ac3
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Showing 3 changed files with 18 additions and 4 deletions.
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
@@ -634,14 +634,12 @@ abstract class Data extends BaseType with SourceInfoDoc {
       case Some(BundleLitBinding(litMap)) =>
         litMap.get(this) match {
           case Some(litArg) => litArg
-          // TODO make a Const once const is supported in firtool
-          case _ => materializeWire() // FIXME FIRRTL doesn't have Bundle literal expressions
+          case _            => materializeWire(true) // FIXME FIRRTL doesn't have Bundle literal expressions
         }
       case Some(VecLitBinding(litMap)) =>
         litMap.get(this) match {
           case Some(litArg) => litArg
-          // TODO make a Const once const is supported in firtool
-          case _ => materializeWire() // FIXME FIRRTL doesn't have Vec literal expressions
+          case _            => materializeWire(true) // FIXME FIRRTL doesn't have Vec literal expressions
         }
       case Some(DontCareBinding()) =>
         materializeWire() // FIXME FIRRTL doesn't have a DontCare expression so materialize a Wire

diff --git a/src/test/scala/chiselTests/BundleLiteralSpec.scala b/src/test/scala/chiselTests/BundleLiteralSpec.scala
@@ -352,4 +352,12 @@ class BundleLiteralSpec extends ChiselFlatSpec with Utils {
       }
     }
   }
+
+  "bundle literals" should "materialize const wires" in {
+    val chirrtl = ChiselStage.emitCHIRRTL(new Module {
+      val r = RegInit((new MyBundle).Lit(_.a -> 42.U, _.b -> true.B, _.c -> MyEnum.sB))
+    })
+    val wire = """wire.*: const \{ a : UInt<8>, b : UInt<1>, c : UInt<1>\}""".r
+    (chirrtl should include).regex(wire)
+  }
 }
diff --git a/src/test/scala/chiselTests/VecLiteralSpec.scala b/src/test/scala/chiselTests/VecLiteralSpec.scala
@@ -507,4 +507,12 @@ class VecLiteralSpec extends ChiselFreeSpec with Utils {
     vec.getWidth should be(16 * 2)
     vec.litValue should be(BigInt("bbbb000a", 16))
   }
+
+  "vec literals should materialize const wires" in {
+    val chirrtl = ChiselStage.emitCHIRRTL(new Module {
+      val r = RegInit(Vec(2, UInt(4.W)).Lit(0 -> 1.U, 1 -> 2.U))
+    })
+    val wire = """wire.*: const UInt<4>\[2\]""".r
+    (chirrtl should include).regex(wire)
+  }
 }