ChiselSim improvements to close the gap to chiseltest

[carlosedp]

ChiselSim Improvements

I started porting some tests from chiseltest to ChiselSim and found some usability gaps that could be improved. Also some error:

• Having a simulator which allows generating VCD Files (Addressed on [ChiselSim] Implement a parametric simulator able to customise simulations #4201)
• Error on some Module and Memory initialization (needs further investigation)
• Have method extensions in the PeekPokeAPI that generates native Scala types like peekLit instead of peek().litValue like sample1.
• Handle ChiselEnum in Peek. Allow something like c.io.DecoderPort.inst.peek() should be(inst) instead of c.io.DecoderPort.inst.peekValue().asBigInt should be(inst.litValue) where inst is a ChiseEnum - (Reported on [ChiselSim] ChiselEnum does not provide peek/poke methods and user-friendly API #4208)
• Have the ability to peek into SubModules like BoringUtils.bore exposed thru chiseltest.experimental.expose like Observe.scala
• Verilator error on tests which have Modules with chisel3.experimental.Analog ports (Modules with chisel3.experimental.Analog ports generate error using ChiselSim #4202)

Refs:

Sample 1:

// Scala 2 extension methods for Chisel Data types converting peek().litValue to peekLit
object ObjectUtils {
  // For UInt and SInt
  implicit class UIntLitValue(u: UInt) {
    def peekLit: BigInt = u.peek().litValue
  }
  implicit class SIntLitValue(s: SInt) {
    def peekLit: BigInt = s.peek().litValue
  }
  // For Bool
  implicit class BoolLitValue(b: Bool) {
    def peekLit: Boolean = b.peek().litToBoolean
  }
}