SRAM API: Add multiple-clocked port API

[jared-barocsi]

It is sometimes desirable to instantiate a memory with ports clocked with different clocks (e.g. clock domain crossing). This PR adds additional APIs to SRAM which allow users to drive ports using a sequence of clocks:

// Create a multi-clocked 3R, 2W SRAM
val mem = SRAM(
  1024, 
  UInt(8.W), 
  Seq(clock1, clock2, clock3), // Memory read port clocks
  Seq(clock4, clock5),         // Memory write port clocks
  Seq.empty                    // Memory read-write port clocks
)

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Type of Improvement

• Feature (or new API)

Desired Merge Strategy

Squash

Release Notes

Add new SRAM APIs that take three Clock sequences as parameters instead of the number of read/write/read-write ports. This will sequentially instantiate a memory port for each clock in the Clock sequence and drive them accordingly.

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[jackkoenig]

Generally looks good, some style suggestions

[jackkoenig]

Is there a real purpose to having 3 parameter lists here? Since this is a private method I would just defined it with a normal single parameter list.

Suggested change

	private def memInterface_impl[T <: Data](
	size: BigInt,
	tpe: T
	)(readPortClocks: Seq[Clock],
	writePortClocks: Seq[Clock],
	readwritePortClocks: Seq[Clock],
	memoryFile: Option[MemoryFile]
	)(evidenceOpt: Option[T <:< Vec[_]],
	sourceInfo: SourceInfo
	private def memInterface_impl[T <: Data](
	size: BigInt,
	tpe: T,
	readPortClocks: Seq[Clock],
	writePortClocks: Seq[Clock],
	readwritePortClocks: Seq[Clock],
	memoryFile: Option[MemoryFile],
	evidenceOpt: Option[T <:< Vec[_]],
	sourceInfo: SourceInfo

[jackkoenig]

Suggested change

	for ((clock, i) <- readPortClocks.zipWithIndex) {
	_out.readPorts(i).data := mem.read(_out.readPorts(i).address, _out.readPorts(i).enable, clock)
	}
	for ((clock, port) <- readPortClocks.zip(_out.readPort)) {
	port.data := mem.read(port.address, port.enable, clock)
	}

I should've caught this with the earlier PR, but unless you are writing performance critical code using Arrays, indexing a Seq is code smell. This same change for the write and readwrite ports will make those loops much cleaner.

[jackkoenig]

Suggested change

	memInterface_impl(size, tpe)(
	Seq.fill(numReadPorts)(Builder.forcedClock),
	Seq.fill(numWritePorts)(Builder.forcedClock),
	Seq.fill(numReadwritePorts)(Builder.forcedClock),
	None
	)(
	Some(evidence),
	sourceInfo
	)
	): SRAMInterface[T] = {
	val clock = Builder.forcedClock
	memInterface_impl(size, tpe)(
	Seq.fill(numReadPorts)(clock),
	Seq.fill(numWritePorts)(clock),
	Seq.fill(numReadwritePorts)(clock),
	None
	)(
	Some(evidence),
	sourceInfo
	)
	}

This would be cleaner with just assigning clock to a val, also that's just generally a good idea because Builder.forcedClock requires accessing the Chisel runtime in the Dynamic variable which is just unnecessary extra compute to do more than once here.

[jackkoenig]

Same suggestion for the other places calling Builder.forcedClock a bunch.

[jackkoenig]

This is fun but maybe too clever by half, it would be more straightforward to just have Vecs of clocks (which are Seqs)

Suggested change

	val (counter, _) = Counter(true.B, 11)
	val clock1: Clock = (counter === 1.U).asClock
	val clock2: Clock = (counter === 2.U).asClock
	val clock3: Clock = (counter === 3.U).asClock
	val readClocks = Seq(clock1, clock2, clock3)
	val writeClocks = Seq(clock2, clock3, clock1)
	val readwriteClocks = Seq(clock3, clock1, clock2)
	val readClocks = IO(Input(Vec(3, Clock())))
	val writeClocks = IO(Input(Vec(3, Clock())))
	val readwriteClocks = IO(Input(Vec(3, Clock())))

Then below you just look for the clocks, eg. readClocks[$i]

[jackkoenig]

Please assign Builder.forcedClock to a val here as well.

[jackkoenig]

Please assign Builder.forcedClock to a val here as well.

[jackkoenig]

LGTM but please address the 2 minor nits