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Instance Annotations, Try No. 2 #926

Merged
merged 64 commits into from Oct 31, 2018
Merged

Instance Annotations, Try No. 2 #926

merged 64 commits into from Oct 31, 2018

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azidar
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@azidar azidar commented Oct 29, 2018

Followup from #925 which was a revert of #865 .

Additionally includes significant performance and memory improvements of the Dedup pass.

@azidar
Added Component, most tests pass
a12d74e
@azidar
Added IRLookup and EliminateComponentPaths
fec7556
@azidar
Cleaned up implementation
57ff7cc
@azidar
Fixed RenameMapSpec
3ccff8f
@azidar
WIP: RenameMap works, now need to fix Dedup
8d06b98
@azidar
Dedup works
289920f
@azidar
Updated tests
f8512cb
@azidar
Tests pass. Needs review and commentary on instance resolution semantics
2ce0345
@azidar
Renamed Component->Target, SubComponent->TargetToken
0706062
@azidar
Removed IRLookup
190dd06
@azidar
Moved BrittleAnnotation to own file
eed45cc
@azidar
Deleted BrittleAnnotation
8e31666
@azidar
Merge branch 'master' into cicl
83d49b2
@azidar
Refactoring names again
0a422e0
@azidar
Merge branch 'cicl' of github.com:freechipsproject/firrtl into cicl
adb8b0a
@azidar
Added tests and fixed bugs
f3bdac9
@azidar
Added another test
00078ba
@azidar
Added more rename tests
18b9657
@azidar
Added caching to get, reduces time from O(3^N) to O(N^3)
4a28f1a
@azidar
forgot to comment out debug code that breaks tests
7e36837
@azidar
Added more tests for RenameMapSpec
b349eca
@azidar
Merge branch 'master' of github.com:freechipsproject/firrtl into cicl
aee9e02
@azidar
Added rename optimization and clearer recursiveGet
52f2057
@azidar
Added type safety to CompleteTargets
c0aef8b
@azidar
Added typesafe Targets, with local/nonlocal types
f1dbba4
@azidar
Tests pass
cce2d3e
@azidar
Removed Locality from types, was too annoying and provided little ben…
66e1106 
…efit. Tests pass
@azidar
Merge branch 'master' of github.com:freechipsproject/firrtl into cicl
2ac4b69
@azidar
Added tests and documentation
e0b0357
@azidar
Added more documentation
5aa3ff9
azidar and others added 21 commits October 16, 2018 18:25
@azidar
Preserve backwards compatibility
6bc0aca
@azidar
Fix rename for backwards compatibility
194b648
@azidar
Merge branch 'master' of github.com:freechipsproject/firrtl into cicl
a9ea5e0
@azidar
Added back get(key:Named)
94e4a35
@azidar
Moved RenameMap to new file. Deprecated RenameMap.apply
8696269
@azidar
Added back passes.VerilogRename for backwards compatibility
d2520c2
@azidar
Added back verilogRenameN for backwards compatibility
86f8ae8
@azidar
Fixed serialization/deserialization
9ba8d9e
@azidar
Removed attempt to fix unapply on DontTouchAnnotation
7507544
@azidar
Small changes for performance
9880eec
@azidar
Bugfix - deleting uninstantiated targets in EliminateTargetPaths
4ef23e2
@azidar
Changed match on List to match on Seq
792472f
@azidar
Made prepare package private
7907736
@jackkoenig
Minimal example showing bug where Inline inserts '.' into a WRef
3b65e59
@azidar
Revert "Minimal example showing bug where Inline inserts '.' into a W…
bcba9b2 
…Ref"

This reverts commit 3b65e59.
@azidar
Bugfix: inline instances relied on ComponentName not renaming properly
dbc5cde
@azidar
Merge branch 'master' into cicl
47dd7fd
@azidar
Added different rename technique for dedup
08f7d0b
@azidar
Merge branch 'cicl' of github.com:freechipsproject/firrtl into cicl
3424e61
@azidar
More performance improvements for dedup
0073294
@azidar
Added a profiling version of firrtl
d621ec9
@azidar azidar requested a review from a team as a code owner October 29, 2018 17:55
@seldridge seldridge mentioned this pull request Oct 29, 2018
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jackkoenig
jackkoenig approved these changes Oct 30, 2018
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I reviewed the performance improvements and they look sane. I have also run this with our internal regression and everything works! I verified that the problematic design runs with these changes with minimal runtime and memory use impact. Nice work!

@azidar azidar merged commit 0a4bcaa into master Oct 31, 2018
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@ucbjrl ucbjrl added this to the 1.2.0 milestone Dec 4, 2018
@albert-magyar albert-magyar deleted the cicl branch May 18, 2020 04:18
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