RVV 0.9 changes #2477
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RVV 0.9 changes #2477
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Member
aswaterman
commented
May 18, 2020
•
aswaterman
commented
- Fractional LMUL
- Tail-agnostic/mask-agnostic bits
- EEW loads/stores
- Some encoding changes
- Add utilities for bitwise shifts by signed shift amounts
| def VLE8_V = BitPat("b???000?00000?????000?????0000111") | ||
| def VLE16_V = BitPat("b???000?00000?????101?????0000111") | ||
| def VLE32_V = BitPat("b???000?00000?????110?????0000111") | ||
| def VLE64_V = BitPat("b???000?00000?????111?????0000111") |
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Why did you define VLE... opcodes for every width instead of single VLE opcode and then extracting the width from instruction bits directly?
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Note all three funct3 bits get used (bit14 is 0 for VLE8, but it’s 1 for the others). This is because FLH/FLW/FLD/FLQ are in the same major opcode. If I replaced funct3 with ???, then VLE would conflict with the FP loads.
Of course this is just for illegal instruction detection. Once you get past that point, I agree you should just extract bits 13:12 to determine the width, rather than treating these as four separate instructions.
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