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RVV 0.9 changes #2477

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merged 4 commits into from
May 19, 2020
Merged

RVV 0.9 changes #2477

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23228b7
Add utils for shifting UInts by signed shift amounts
aswaterman May 12, 2020
df50c61
Implement RVV v0.9 fractional LMUL scheme
aswaterman May 12, 2020
ba8419d
RVV v0.9 opcode changes
aswaterman May 12, 2020
39291a2
Reset VL register for consistency with reset value vtype.vill
aswaterman May 14, 2020
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39 changes: 26 additions & 13 deletions src/main/scala/rocket/CSR.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -246,40 +246,52 @@ class VConfig(implicit p: Parameters) extends CoreBundle {
}

object VType {
private def fromUInt(that: UInt, ignore_vill: Boolean)(implicit p: Parameters): VType = {
def fromUInt(that: UInt, ignore_vill: Boolean = false)(implicit p: Parameters): VType = {
val res = 0.U.asTypeOf(new VType)
val in = that.asTypeOf(res)
res.vill := (in.max_vsew < in.vsew) || in.reserved =/= 0 || in.vill
when (!res.vill || ignore_vill) {
val vill = (in.max_vsew < in.vsew) || !in.lmul_ok || in.reserved =/= 0 || in.vill
when (!vill || ignore_vill) {
res := in
res.vsew := in.vsew(log2Ceil(1 + in.max_vsew) - 1, 0)
res.vlmul := in.vlmul
}
res.reserved := 0.U
res.vill := vill
res
}

def fromUInt(that: UInt)(implicit p: Parameters): VType = fromUInt(that, false)

def computeVL(avl: UInt, vtype: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool)(implicit p: Parameters): UInt =
VType.fromUInt(vtype, true).vl(avl, currentVL, useCurrentVL, useMax, useZero)
}

class VType(implicit p: Parameters) extends CoreBundle {
val vill = Bool()
val reserved = UInt((xLen - 6).W)
val reserved = UInt((xLen - 9).W)
val vma = Bool()
val vta = Bool()
val vlmul_sign = Bool()
val vsew = UInt(3.W)
val vlmul = UInt(2.W)
val vlmul_mag = UInt(2.W)

def vlmul_signed: SInt = Cat(vlmul_sign, vlmul_mag).asSInt

@deprecated("use vlmul_sign, vlmul_mag, or vlmul_signed", "RVV 0.9")
def vlmul: UInt = vlmul_mag

def max_vsew = log2Ceil(eLen/8)
def max_vlmul = (1 << vlmul_mag.getWidth) - 1

def lmul_ok: Bool = (!this.vlmul_sign || this.vlmul_mag =/= 0) &&
(this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag) <= maxVLMax.log2)

val max_vsew = log2Ceil(eLen/8)
def minVLMax: Int = ((maxVLMax / eLen) >> ((1 << vlmul_mag.getWidth) - 1)) max 1

def minVLMax = maxVLMax / eLen
def vlMax: UInt = (maxVLMax >> (this.vsew +& ~this.vlmul)).andNot(minVLMax-1)
def vlMaxInBytes: UInt = maxVLMax >> ~this.vlmul
def vlMax: UInt = (maxVLMax >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).andNot(minVLMax-1)

def vl(avl: UInt, currentVL: UInt, useCurrentVL: Bool, useMax: Bool, useZero: Bool): UInt = {
val atLeastMaxVLMax = useMax || Mux(useCurrentVL, currentVL >= maxVLMax, avl >= maxVLMax)
val avl_lsbs = Mux(useCurrentVL, currentVL, avl)(maxVLMax.log2 - 1, 0)

val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& ~this.vlmul)).asUInt.andNot(minVLMax-1)).orR
val atLeastVLMax = atLeastMaxVLMax || (avl_lsbs & (-maxVLMax.S >> (this.vsew +& Cat(this.vlmul_sign, ~this.vlmul_mag))).asUInt.andNot(minVLMax-1)).orR
val isZero = vill || useZero
Mux(!isZero && atLeastVLMax, vlMax, 0.U) | Mux(!isZero && !atLeastVLMax, avl_lsbs, 0.U)
}
Expand Down Expand Up @@ -995,6 +1007,7 @@ class CSRFile(
vio.vxrm := reg_vxrm.get

when (reset.toBool) {
reg_vconfig.get.vl := 0.U
reg_vconfig.get.vtype := 0.U.asTypeOf(new VType)
reg_vconfig.get.vtype.vill := true
}
Expand Down