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Linter syntax error wrong detection #1542

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gmlarumbe opened this issue Nov 28, 2022 · 1 comment
Open

Linter syntax error wrong detection #1542

gmlarumbe opened this issue Nov 28, 2022 · 1 comment
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style-linter Verilog style-linter issues

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@gmlarumbe
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Hi,

The verible-verilog-lint tool detects a syntax error in the wrong line (version v0.0-2492-gd122fac8).

Given the following file (test_preprocessing.sv), the error is in line 4 but it is detected in the undefined UVM macro of line 2 instead:

class test_component extends uvm_component;
    `uvm_component_utils(test_component)

    syntax_error;

    function new(string name="test_component", uvm_component parent);
        super.new(name, parent);
    endfunction : new

endclass: test_component

Running the following command:

$ ~/bin/verible-v0.0-2492-gd122fac8/bin/verible-verilog-lint test_preprocessing.sv
test_preprocessing.sv:2:5-24: preprocessing error at token "`uvm_component_utils" : Error expanding macro identifier, might not be defined before.

However, with previous version v0.0-2080-gc9674d91 the error was detected correctly:

$ ~/bin/verible-v0.0-2080-gc9674d91/bin/verible-verilog-lint test_preprocessing.sv
test_preprocessing.sv:4:17: syntax error at token ";"

Fixing the syntax error yields no output with version v0.0-2492-gd122fac8, e.g.:

class test_component extends uvm_component;
    `uvm_component_utils(test_component)

    no_syntax_error variable;

    function new(string name="test_component", uvm_component parent);
        super.new(name, parent);
    endfunction : new

endclass: test_component

Thanks!

@gmlarumbe gmlarumbe added the style-linter Verilog style-linter issues label Nov 28, 2022
@matlupi
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matlupi commented Dec 7, 2023

I did run the same example above on the revisions below and it appears it has not been fixed yet.

On v0.0-2884-g42c9491b

  • the file with the syntax error at line 4 returns a problem in the UVM macro
  • the file without the syntax error returns 0

On v0.0-3430-g060bde0f

  • the file with the syntax error at line 4 returns a problem in the UVM macro
  • the file without the syntax error returns 0

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Labels
style-linter Verilog style-linter issues
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