You signed in with another tab or window. Reload to refresh your session.You signed out in another tab or window. Reload to refresh your session.You switched accounts on another tab or window. Reload to refresh your session.Dismiss alert
$ ~/bin/verible-v0.0-2492-gd122fac8/bin/verible-verilog-lint test_preprocessing.sv
test_preprocessing.sv:2:5-24: preprocessing error at token "`uvm_component_utils" : Error expanding macro identifier, might not be defined before.
However, with previous version v0.0-2080-gc9674d91 the error was detected correctly:
$ ~/bin/verible-v0.0-2080-gc9674d91/bin/verible-verilog-lint test_preprocessing.sv
test_preprocessing.sv:4:17: syntax error at token ";"
Fixing the syntax error yields no output with version v0.0-2492-gd122fac8, e.g.:
Hi,
The
verible-verilog-lint
tool detects a syntax error in the wrong line (version v0.0-2492-gd122fac8).Given the following file (test_preprocessing.sv), the error is in line 4 but it is detected in the undefined UVM macro of line 2 instead:
Running the following command:
However, with previous version v0.0-2080-gc9674d91 the error was detected correctly:
Fixing the syntax error yields no output with version v0.0-2492-gd122fac8, e.g.:
Thanks!
The text was updated successfully, but these errors were encountered: