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Merge python3-rc2 branch into master #656

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merged 40 commits into from Aug 15, 2019
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4642052
Make Exceptions work with python 2/3
BrentHoltsclaw Jul 18, 2018
c3685be
Cleaned up print statements to support python 2/3
BrentHoltsclaw Jul 17, 2018
4980337
Python 3 Compatability changes
BrentHoltsclaw Jul 18, 2018
164aca4
update copyright info
BrentHoltsclaw Dec 10, 2018
005eb88
Started converstion of % to format
BrentHoltsclaw Jul 27, 2018
5f97ea8
cleanup
BrentHoltsclaw Jul 27, 2018
d948ec2
Changed more files
BrentHoltsclaw Sep 10, 2018
f5b0c43
inital pass through all files
BrentHoltsclaw Sep 11, 2018
45e872d
minor cleanup
BrentHoltsclaw Sep 11, 2018
782ade3
change hal.spi
BrentHoltsclaw Sep 11, 2018
97cd395
fixes after general windows testing
BrentHoltsclaw Sep 13, 2018
95a430e
Edits made to satisfy comments
BrentHoltsclaw Oct 2, 2018
fbe509a
Changes based upon @Frinzell comments
BrentHoltsclaw Dec 19, 2018
beac2c8
Remove metaclass from oshelpers.py
BrentHoltsclaw Dec 19, 2018
d51eb62
Cleanup modules so that chipsec_main.py can be run
BrentHoltsclaw Jan 9, 2019
77e7f57
Cleanup modules so that chipsec_util.py can be run
BrentHoltsclaw Jan 9, 2019
4d3af6b
Fixes for ACPI chipsec_util command
BrentHoltsclaw Jan 14, 2019
efedaf1
Fixes for CPU chipsec_util command
BrentHoltsclaw Jan 14, 2019
dffc5d9
Fixes for DELTAS chipsec_util command
BrentHoltsclaw Jan 14, 2019
8be0888
Fixes for IGD chipsec_util command
BrentHoltsclaw Jan 14, 2019
b5c3cd7
Fixes for MEM chipsec_util command
BrentHoltsclaw Jan 14, 2019
a33d7e4
Fixes for VMEM chipsec_util command
BrentHoltsclaw Jan 14, 2019
a63096a
Fix chipsec_util command UEFI
BrentHoltsclaw Feb 6, 2019
9d3461e
Changes for SPI and SPI Descriptor Util commands
BrentHoltsclaw Feb 8, 2019
d17d265
Fixes for unittest to work within python3 and python2
BrentHoltsclaw Apr 4, 2019
c6e5e5b
Fixes to get things working after rebase with master
BrentHoltsclaw May 14, 2019
350332a
Add signed guid Certificate RSA2048/SHA256 support to UEFI decompress
BrentHoltsclaw May 20, 2019
b8e0769
Changes to get chipsec_util and chipsec_main working within python3
BrentHoltsclaw May 24, 2019
b3c552b
Issue #581 LZMA decompress failing
BrentHoltsclaw May 29, 2019
fe7a202
fix exception handling, tuple isn't allowed anymore. Also, pywintypes…
NicholasArmour May 31, 2019
671f5a7
unicode to keep python2 happy. This doesn't seem to break python3
NicholasArmour May 31, 2019
69ab324
ok, unicode DOES break python3, need to check version and handle appr…
NicholasArmour Jun 3, 2019
5e727f1
rename nested exception
NicholasArmour Jun 6, 2019
919224a
macOS fixes to run chipsec_main with python3
BrentHoltsclaw Jun 10, 2019
35233f5
Pylint cleanup of hal modules
User942blib Jun 18, 2019
aae3746
Update hal.paging to pass pylint
BrentHoltsclaw Jun 18, 2019
93a1659
Fix pylint errors within utilcmds
User942blib Jun 19, 2019
b4beadc
Cleanup pylint errors within the chipsec/helper directory
User942blib Jun 17, 2019
fdb0e86
Merge pull request #639 from BrentHoltsclaw/python3-rc2-1
BrentHoltsclaw Jul 29, 2019
cc7b050
Changes to update code based upon feedback
BrentHoltsclaw Aug 14, 2019
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20 changes: 14 additions & 6 deletions .travis.yml
@@ -1,6 +1,4 @@
language: python
python:
- 2.7
sudo: required
install:
- sudo apt-get -qq update
Expand All @@ -9,12 +7,22 @@ install:

matrix:
include:
- name: "Trusty"
- name: "Trusty - python2"
os: linux
dist: trusty
- name: "Xenial"
python: 2.7
- name: "Xenial - python2"
os: linux
dist: xenial
dist: xenial
python: 2.7
- name: "Trusty - python3"
os: linux
dist: trusty
python: 3.5
- name: "Xenial - python3"
os: linux
dist: xenial
python: 3.5
- name: "MacOS Build"
os : osx
language: generic
Expand All @@ -23,4 +31,4 @@ matrix:
- brew install nasm

script:
- python setup.py test
- python setup.py test
2 changes: 1 addition & 1 deletion chipsec/VERSION
@@ -1 +1 @@
1.3.8
1.3.8
64 changes: 32 additions & 32 deletions chipsec/chipset.py
Expand Up @@ -338,7 +338,7 @@ def print_supported_chipsets():
logger().log( "-------------------------------------------------------------------------------------" )
for _code in sorted(codes_dict):
for _did in codes_dict[_code]:
logger().log( " %-#6x | %-14s | %-6s | %-40s" % (_did, Chipset_Dictionary[_did]['name'], _code.lower(), Chipset_Dictionary[_did]['longname']) )
logger().log( " {:-#6x} | {:14} | {:6} | {:40}".format(_did, Chipset_Dictionary[_did]['name'], _code.lower(), Chipset_Dictionary[_did]['longname']) )


def f_xml(self, x):
Expand Down Expand Up @@ -436,15 +436,15 @@ def init( self, platform_code, req_pch_code, start_driver, driver_exists=None, t

_unknown_platform = False
self.helper.start(start_driver, driver_exists, to_file, from_file)
logger().log( '[CHIPSEC] API mode: %s' % ('using OS native API (not using CHIPSEC kernel module)' if self.use_native_api() else 'using CHIPSEC kernel module API') )
logger().log( '[CHIPSEC] API mode: {}'.format('using OS native API (not using CHIPSEC kernel module)' if self.use_native_api() else 'using CHIPSEC kernel module API') )

self.vid, self.did, self.rid, self.pch_vid, self.pch_did, self.pch_rid = self.detect_platform()
if platform_code is None:
if VID_INTEL != self.vid:
_unknown_platform = True
else:
self.vid = VID_INTEL
if Chipset_Code.has_key( platform_code ):
if platform_code in Chipset_Code:
self.did = Chipset_Code[ platform_code ]
self.rid = 0x00
else:
Expand All @@ -453,7 +453,7 @@ def init( self, platform_code, req_pch_code, start_driver, driver_exists=None, t
self.did = 0xFFFF
self.rid = 0xFF

if Chipset_Dictionary.has_key( self.did ):
if self.did in Chipset_Dictionary:
data_dict = Chipset_Dictionary[ self.did ]
self.code = data_dict['code'].lower()
self.longname = data_dict['longname']
Expand All @@ -464,15 +464,15 @@ def init( self, platform_code, req_pch_code, start_driver, driver_exists=None, t

if req_pch_code is not None:
self.pch_vid = VID_INTEL
if pch_codes.has_key(req_pch_code):
if req_pch_code in pch_codes:
self.pch_did = pch_codes[req_pch_code]
self.pch_rid = 0x00
else:
self.pch_vid = 0xFFFF
self.pch_did = 0xFFFF
self.pch_rid = 0xFF

if self.pch_vid == VID_INTEL and pch_dictionary.has_key(self.pch_did):
if self.pch_vid == VID_INTEL and self.pch_did in pch_dictionary:
data_dict = pch_dictionary[self.pch_did]
self.pch_code = data_dict['code'].lower()
self.pch_longname = data_dict['longname']
Expand All @@ -484,7 +484,7 @@ def init( self, platform_code, req_pch_code, start_driver, driver_exists=None, t
if _unknown_platform and start_driver:
msg = 'Unsupported Platform: VID = 0x{:04X}, DID = 0x{:04X}, RID = 0x{:02X}'.format(self.vid,self.did,self.rid)
logger().error( msg )
raise UnknownChipsetError, msg
raise UnknownChipsetError (msg)


def destroy( self, start_driver ):
Expand Down Expand Up @@ -583,14 +583,14 @@ def init_xml_configuration( self ):
def init_cfg_xml(self, fxml, code, pch_code):
import xml.etree.ElementTree as ET
if not os.path.exists( fxml ): return
if logger().DEBUG: logger().log( "[*] looking for platform config in '%s'.." % fxml )
if logger().DEBUG: logger().log( "[*] looking for platform config in '{}'..".format(fxml) )
tree = ET.parse( fxml )
root = tree.getroot()
for _cfg in root.iter('configuration'):
if 'platform' not in _cfg.attrib:
if logger().DEBUG: logger().log( "[*] loading common platform config from '%s'.." % fxml )
if logger().DEBUG: logger().log( "[*] loading common platform config from '{}'..".format(fxml) )
elif code == _cfg.attrib['platform'].lower():
if logger().DEBUG: logger().log( "[*] loading '%s' platform config from '%s'.." % (code,fxml) )
if logger().DEBUG: logger().log( "[*] loading '{}' platform config from '{}'..".format(code,fxml) )
elif pch_code == _cfg.attrib['platform'].lower():
if logger().DEBUG: logger().log("[*] loading '{}' PCH config from '{}'..".format(pch_code,fxml))
else: continue
Expand All @@ -606,7 +606,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
self.Cfg.CONFIG_PCI.pop(_name, None)
continue
self.Cfg.CONFIG_PCI[ _name ] = _device.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _device.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _device.attrib) )
if logger().DEBUG: logger().log( "[*] loading MMIO BARs.." )
for _mmio in _cfg.iter('mmio'):
for _bar in _mmio.iter('bar'):
Expand All @@ -618,7 +618,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
self.Cfg.MMIO_BARS.pop(_name, None)
continue
self.Cfg.MMIO_BARS[ _name ] = _bar.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _bar.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _bar.attrib) )
if logger().DEBUG: logger().log( "[*] loading I/O BARs.." )
for _io in _cfg.iter('io'):
for _bar in _io.iter('bar'):
Expand All @@ -630,7 +630,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
self.Cfg.IO_BARS.pop(_name, None)
continue
self.Cfg.IO_BARS[ _name ] = _bar.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _bar.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _bar.attrib) )
if logger().DEBUG: logger().log( "[*] loading memory ranges.." )
for _memory in _cfg.iter('memory'):
for _range in _memory.iter('range'):
Expand All @@ -642,7 +642,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
self.Cfg.MEMORY_RANGES.pop(_name, None)
continue
self.Cfg.MEMORY_RANGES[ _name ] = _range.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _range.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _range.attrib) )
if logger().DEBUG: logger().log( "[*] loading configuration registers.." )
for _registers in _cfg.iter('registers'):
for _register in _registers.iter('register'):
Expand All @@ -664,7 +664,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
reg_fields[ _field_name ] = _field.attrib
_register.attrib['FIELDS'] = reg_fields
self.Cfg.REGISTERS[ _name ] = _register.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _register.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _register.attrib) )
if logger().DEBUG: logger().log( "[*] loading controls.." )
for _controls in _cfg.iter('controls'):
for _control in _controls.iter('control'):
Expand All @@ -676,7 +676,7 @@ def init_cfg_xml(self, fxml, code, pch_code):
self.Cfg.CONTROLS.pop(_name, None)
continue
self.Cfg.CONTROLS[ _name ] = _control.attrib
if logger().DEBUG: logger().log( " + %-16s: %s" % (_name, _control.attrib) )
if logger().DEBUG: logger().log( " + {:16}: {}".format(_name, _control.attrib) )

def init_cfg_bus( self ):
if logger().DEBUG: logger().log( '[*] loading device buses..' )
Expand All @@ -703,10 +703,10 @@ def init_cfg(self):
try:
module_path = 'chipsec.cfg.' + self.code
module = importlib.import_module( module_path )
logger().log_good( "imported platform specific configuration: chipsec.cfg.%s" % self.code )
logger().log_good( "imported platform specific configuration: chipsec.cfg.{}".format(self.code) )
self.Cfg = getattr( module, self.code )()
except ImportError, msg:
if logger().DEBUG: logger().log( "[*] Couldn't import chipsec.cfg.%s\n%s" % ( self.code, str(msg) ) )
except ImportError as msg:
if logger().DEBUG: logger().log( "[*] Couldn't import chipsec.cfg.{}\n{}".format( self.code, str(msg) ) )

#
# Initialize platform configuration from XML files
Expand All @@ -727,7 +727,7 @@ def init_cfg(self):

def get_device_BDF( self, device_name ):
device = self.Cfg.CONFIG_PCI[ device_name ]
if device is None or device == {}: raise DeviceNotFoundError, ('DeviceNotFound: %s' % device_name)
if device is None or device == {}: raise DeviceNotFoundError ('DeviceNotFound: {}'.format(device_name))
b = int(device['bus'],16)
d = int(device['dev'],16)
f = int(device['fun'],16)
Expand Down Expand Up @@ -776,8 +776,8 @@ def is_register_defined(self, reg_name):
try:
return (self.Cfg.REGISTERS[reg_name] is not None)
except KeyError:
#if logger().DEBUG: logger().error( "'%s' register definition not found in XML config" % reg_name)
#raise RegisterNotFoundError, ('RegisterNotFound: %s' % reg_name)
#if logger().DEBUG: logger().error( "'{}' register definition not found in XML config".format(reg_name))
#raise RegisterNotFoundError, ('RegisterNotFound: {}'.format(reg_name))
return False

def get_register_def(self, reg_name, bus_index=0):
Expand Down Expand Up @@ -929,7 +929,7 @@ def read_register_field( self, reg_name, field_name, preserve_field_position=Fal
def write_register_field( self, reg_name, field_name, field_value, preserve_field_position=False, cpu_thread=0 ):
reg_value = self.read_register(reg_name, cpu_thread)
reg_value_new = self.set_register_field(reg_name, reg_value, field_name, field_value, preserve_field_position)
#logger().log("set register %s (0x%x) field %s = 0x%x ==> 0x%x" % (reg_name, reg_value, field_name, field_value, reg_value_new))
#logger().log("set register {} (0x{:x}) field {} = 0x{:x} ==> 0x{:x}".format(reg_name, reg_value, field_name, field_value, reg_value_new))
return self.write_register(reg_name, reg_value_new, cpu_thread)

def register_has_field( self, reg_name, field_name ):
Expand All @@ -953,7 +953,7 @@ def _register_fields_str(self, reg_def, reg_val):
field_mask = (field_mask << 1) | 1
field_value = (reg_val >> field_bit) & field_mask
field_desc = (' << ' + field_attrs['desc'] + ' ') if (field_attrs['desc'] != '') else ''
reg_fields_str += (" [%02d] %-16s = %X%s\n" % (field_bit,f[0],field_value,field_desc))
reg_fields_str += (" [{:02d}] {:16} = {:X}{}\n".format(field_bit,f[0],field_value,field_desc))

if '' != reg_fields_str: reg_fields_str = reg_fields_str[:-1]
return reg_fields_str
Expand All @@ -962,26 +962,26 @@ def print_register(self, reg_name, reg_val, bus_index=0):
reg = self.get_register_def( reg_name, bus_index )
rtype = reg['type']
reg_str = ''
reg_val_str = ("0x%0" + ("%dX" % (int(reg['size'],16)*2))) % reg_val
reg_val_str = "0x{:{width}X}".format(reg_val,width=(int(reg['size'],16)*2))
if RegisterType.PCICFG == rtype or RegisterType.MMCFG == rtype:
b = int(reg['bus'],16)
d = int(reg['dev'],16)
f = int(reg['fun'],16)
o = int(reg['offset'],16)
mmcfg_off_str = ''
if RegisterType.MMCFG == rtype:
mmcfg_off_str += ", MMCFG + 0x%X" % ((b*32*8 + d*8 + f) * 0x1000 + o)
reg_str = "[*] %s = %s << %s (b:d.f %02d:%02d.%d + 0x%X%s)" % (reg_name, reg_val_str, reg['desc'], b, d, f, o, mmcfg_off_str)
mmcfg_off_str += ", MMCFG + 0x{:X}".format((b*32*8 + d*8 + f) * 0x1000 + o)
reg_str = "[*] {} = {} << {} (b:d.f {:02d}:{:02d}.{:d} + 0x{:X}{})".format(reg_name, reg_val_str, reg['desc'], b, d, f, o, mmcfg_off_str)
elif RegisterType.MMIO == rtype:
reg_str = "[*] %s = %s << %s (%s + 0x%X)" % (reg_name, reg_val_str, reg['desc'], reg['bar'], int(reg['offset'],16))
reg_str = "[*] {} = {} << {} ({} + 0x{:X})".format(reg_name, reg_val_str, reg['desc'], reg['bar'], int(reg['offset'],16))
elif RegisterType.MSR == rtype:
reg_str = "[*] %s = %s << %s (MSR 0x%X)" % (reg_name, reg_val_str, reg['desc'], int(reg['msr'],16))
reg_str = "[*] {} = {} << {} (MSR 0x{:X})".format(reg_name, reg_val_str, reg['desc'], int(reg['msr'],16))
elif RegisterType.PORTIO == rtype:
reg_str = "[*] %s = %s << %s (I/O port 0x%X)" % (reg_name, reg_val_str, reg['desc'], int(reg['port'],16))
reg_str = "[*] {} = {} << {} (I/O port 0x{:X})".format(reg_name, reg_val_str, reg['desc'], int(reg['port'],16))
elif RegisterType.IOBAR == rtype:
reg_str = "[*] %s = %s << %s (I/O %s + 0x%X)" % (reg_name, reg_val_str, reg['desc'], reg['bar'], int(reg['offset'],16))
reg_str = "[*] {} = {} << {} (I/O {} + 0x{:X})".format(reg_name, reg_val_str, reg['desc'], reg['bar'], int(reg['offset'],16))
elif RegisterType.MSGBUS == rtype or RegisterType.MM_MSGBUS == rtype:
reg_str = "[*] %s = %s << %s (msgbus port 0x%X, off 0x%X)" % (reg_name, reg_val_str, reg['desc'], int(reg['port'],16), int(reg['offset'],16))
reg_str = "[*] {} = {} << {} (msgbus port 0x{:X}, off 0x{:X})".format(reg_name, reg_val_str, reg['desc'], int(reg['port'],16), int(reg['offset'],16))

reg_str += self._register_fields_str(reg, reg_val)
logger().log( reg_str )
Expand Down
6 changes: 6 additions & 0 deletions chipsec/defines.py
Expand Up @@ -166,6 +166,12 @@ def DQ(val):
8: 'Q'
}

def bytestostring(mbytes):
if type(mbytes) == type(bytes()):
return mbytes.decode("latin_1")
else:
return mbytes

def pack1(value, size):
"""Shortcut to pack a single value into a string based on its size."""
return struct.pack(SIZE2FORMAT[size], value)
Expand Down
12 changes: 7 additions & 5 deletions chipsec/file.py
Expand Up @@ -53,7 +53,7 @@ def read_file( filename, size=0 ):
try:
f = open(filename, 'rb')
except:
logger().error( "Unable to open file '%.256s' for read access" % filename )
logger().error( "Unable to open file '{:.256}' for read access".format(filename) )
return 0

if size:
Expand All @@ -62,23 +62,25 @@ def read_file( filename, size=0 ):
_file = f.read()
f.close()

if logger().DEBUG: logger().log( "[file] read %d bytes from '%.256s'" % ( len(_file), filename ) )
if logger().DEBUG: logger().log( "[file] read {:d} bytes from '{:256}'".format( len(_file), filename ) )
return _file

def write_file( filename, buffer, append=False ):
#with open( filename, 'wb' ) as f:
# f.write( buffer )
#f.closed
perm = 'ab' if append else 'wb'
perm = 'a' if append else 'w'
if isinstance(buffer,bytes) or isinstance(buffer,bytearray):
perm += 'b'
try:
f = open(filename, perm)
except:
logger().error( "Unable to open file '%.256s' for write access" % filename )
logger().error( "Unable to open file '{:.256}' for write access".format(filename) )
return 0
f.write( buffer )
f.close()

if logger().DEBUG: logger().log( "[file] wrote %d bytes to '%.256s'" % ( len(buffer), filename ) )
if logger().DEBUG: logger().log( "[file] wrote {:d} bytes to '{:.256}'".format( len(buffer), filename ) )
return True


Expand Down