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Add Xilinx tdpbram to clash-cores #2442

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merged 3 commits into from
Apr 18, 2023
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@martijnbastiaan martijnbastiaan commented Mar 22, 2023

Still TODO:

  • Write a changelog entry (see changelog/README.md)
  • Check copyright notices are up to date in edited files
  • Improve documentation
  • Add tests to clash-testsuite
  • Reject negedge active domains? (Read docs)

@martijnbastiaan martijnbastiaan force-pushed the add-xilinx-tdpbram branch 3 times, most recently from f86857e to a403423 Compare March 22, 2023 15:26
@martijnbastiaan martijnbastiaan force-pushed the add-xilinx-tdpbram branch 2 times, most recently from d34d93e to 891e8da Compare March 31, 2023 13:40
@martijnbastiaan martijnbastiaan marked this pull request as ready for review March 31, 2023 13:43
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This is a nice improvement!

I do have some change requests and things I'd like to note. In fact, more than I have time for now, and I need to finish for the day. This is a partial review. I'm afraid GitHub loses my comments if I don't submit them now; I've had problems with it before. So here is part 1.

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Still not quite done, but it's Easter. I didn't make it...

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@martijnbastiaan martijnbastiaan force-pushed the add-xilinx-tdpbram branch 3 times, most recently from 04688a6 to 9a91834 Compare April 12, 2023 08:35
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martijnbastiaan commented Apr 12, 2023

@DigitalBrains1 Thanks for all the comments! I think I've squashed them all now. I've removed the trailing dots, but I do feel like this is a weird rule to have (see #2442 (comment)). Open coverstations:

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@DigitalBrains1 Resolved the last few conversations, and fixed the CI error caused by a new hashable release. Should be good now?

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As discussed

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We did this in a pair review

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@DigitalBrains1 Given the amount of effort you've put in, I've added you as co-author. Thanks for catching that glaring writeRam issue.

Also:

*TdpBlockRam> runUntil id normalWritesTB
Signal sampled for 23 cycles until value True
*TdpBlockRam> runUntil id writeEnableWritesTB
Signal sampled for 18 cycles until value True

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We discovered some more things...

clash-cores/test/Test/Cores/Xilinx/BlockRam.hs Outdated Show resolved Hide resolved
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We discovered some more things...

Why can't I add the ":sob:" emoji to that message!

martijnbastiaan and others added 3 commits April 18, 2023 14:15
Paves the way for adding a true dual port block RAM with byte enables to
`clash-cores`. It adds a new data type with smart constructors called
'MaybeX', which helps programmers deal with 'XException' in their
modelling code.

Fixes #2438
Fixes #2351
Fixes #2350

Co-authored-by: Peter Lebbing <peter@digitalbrains.com>
Co-authored-by: Peter Lebbing <peter@digitalbrains.com>
@martijnbastiaan martijnbastiaan merged commit 95ee5b9 into master Apr 18, 2023
@martijnbastiaan martijnbastiaan deleted the add-xilinx-tdpbram branch April 18, 2023 12:52
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3 participants