Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Various improvements to CSC local trigger emulator #25165

Merged
merged 28 commits into from
Nov 29, 2018
Merged
Show file tree
Hide file tree
Changes from 24 commits
Commits
Show all changes
28 commits
Select commit Hold shift + click to select a range
62539a1
Make all CSC processors and TMBs inherit from common baseboard
Aug 21, 2018
440cd3f
Enable upgrade processors
Oct 5, 2018
9a42f6a
Fixed a bug in CSCBaseboard
tahuang1991 Oct 11, 2018
747ade3
slightly changes the cross bx algorihtm in ME11 motherboard.
tahuang1991 Oct 12, 2018
75ffbe1
Add the case for ME2/1 TMB without GEMs
Oct 12, 2018
22b2e20
add some debugging information in emulator
tahuang1991 Oct 16, 2018
de33840
1. allow same wiregroup triggered twice with some dead time between
tahuang1991 Oct 18, 2018
368bb18
move the localized dead time zone to pretrigger level
tahuang1991 Oct 18, 2018
9339bda
optimized logtrace in CSCTriggerPrimitivesBuilder
tahuang1991 Oct 18, 2018
23022d6
AnodeLCTProcessor: fix a bug in ghost cancellation logic
tahuang1991 Oct 19, 2018
4b81469
fix a bugs in ALCT ghost cancellation logic and CLCT localized dead t…
tahuang1991 Oct 20, 2018
e05f723
fix bug in CSCTriggerPrimitivesReader.cc
tahuang1991 Oct 23, 2018
97ac54a
1. fixed the dead time issue in AnodeLCTProcessor
tahuang1991 Nov 8, 2018
e61d057
Update configs for Phase-2
Nov 8, 2018
7d3ea02
Apply suggestions by code-checks
Nov 8, 2018
c406a1c
Fix ClangBuild errors
Nov 13, 2018
639e857
Fix ClangBuild errors
Nov 13, 2018
1ce58b4
Fix different TMB options
Nov 14, 2018
5da7950
Fix ClangBuild errors
Nov 14, 2018
d97d835
fixed the halfstrip range in ME1a for halfstrip to gem pad LUT
tahuang1991 Nov 14, 2018
b77d9fd
1. fixed a bug in CSCCathodeLCTProcessor to avoid logic bug in a loop
tahuang1991 Nov 15, 2018
ec7ec66
remove comment-out code
tahuang1991 Nov 15, 2018
ce28408
update the comment about why CLCTs in bx0 or 1 usually could be dropp…
tahuang1991 Nov 15, 2018
ac2848a
Fix ClangBuild warnings
Nov 16, 2018
5a24207
Fix includes. Remove refs to very old TMB options. Indentation
Nov 21, 2018
a829bb9
Cleanup
Nov 21, 2018
aa53e5b
Modernize for loops
Nov 21, 2018
d4bc574
Fix static warnings
Nov 23, 2018
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
13 changes: 9 additions & 4 deletions L1Trigger/CSCCommonTrigger/interface/CSCConstants.h
Original file line number Diff line number Diff line change
Expand Up @@ -40,7 +40,10 @@ class CSCConstants
// All ME1A readout by 3 CFEBs -> 3*32 -1
MAX_HALF_STRIP_ME1A_UNGANGED = 95,
// All ME1B readout by 4 CFEBs -> 4*32 -1
MAX_HALF_STRIP_ME1B = 127
MAX_HALF_STRIP_ME1B = 127,
MAX_NUM_STRIPS_ME1B = 64,
MAX_NUM_STRIPS_ME1A_GANGED = 16,
MAX_NUM_STRIPS_ME1A_UNGANGED = 48,
};

// CSCs have 6 layers. The key (refernce) layer is the third layer
Expand Down Expand Up @@ -71,11 +74,13 @@ class CSCConstants
MAX_CLCT_TBINS = 16,
MAX_ALCT_TBINS = 16,
MAX_LCT_TBINS = 16,
// Each CLCT processor can snd up to 2 CLCTs to TMB
// Maximum allowed matching window size
MAX_MATCH_WINDOW_SIZE = 15,
// Each CLCT processor can send up to 2 CLCTs to TMB per BX
MAX_CLCTS_PER_PROCESSOR = 2,
// Each ALCT processor can snd up to 2 ALCTs to TMB
// Each ALCT processor can send up to 2 ALCTs to TMB per BX
MAX_ALCTS_PER_PROCESSOR = 2,
// Each CSC can send up to 2 LCTs to the MPC.
// Each CSC can send up to 2 LCTs to the MPC per BX
MAX_LCTS_PER_CSC = 2,
// An MPC receives up to 18 LCTs from 9 CSCs in the trigger sector
MAX_LCTS_PER_MPC = 18,
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -47,7 +47,6 @@ class CSCTriggerPrimitivesProducer : public edm::global::EDProducer<edm::StreamC
explicit CSCTriggerPrimitivesProducer(const edm::ParameterSet&);
~CSCTriggerPrimitivesProducer() override;

//virtual void beginRun(const edm::EventSetup& setup);
void produce(edm::StreamID, edm::Event&, const edm::EventSetup&) const override;

private:
Expand Down
Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,14 @@

# Parameters common for all boards
commonParam = cms.PSet(
# Flag for SLHC studies (upgraded ME11, MPC)
# Master flag for SLHC studies
isSLHC = cms.bool(False),

# Debug
verbosity = cms.int32(0),

## Whether or not to use the SLHC ALCT algorithm
enableAlctSLHC = cms.bool(False),

## During Run-1, ME1a strips were triple-ganged
## Effectively, this means there were only 16 strips
Expand All @@ -34,6 +40,11 @@

# offset between the ALCT and CLCT central BX in simulation
alctClctOffset = cms.uint32(1),

runME11Up = cms.bool(False),
runME21Up = cms.bool(False),
runME31Up = cms.bool(False),
runME41Up = cms.bool(False),
),

# Parameters for ALCT processors: 2007 and later
Expand Down Expand Up @@ -145,8 +156,8 @@
clctDriftDelay = cms.uint32(2),
clctNplanesHitPretrig = cms.uint32(3),
clctNplanesHitPattern = cms.uint32(4),
# increase pattern ID threshold from 2 to 4 to trigger higher pt tracks
clctPidThreshPretrig = cms.uint32(4),
# increase pattern ID threshold from 2 to 4 to trigger higher pt tracks,ignored--Tao
clctPidThreshPretrig = cms.uint32(2),
# decrease possible minimal #HS distance between two CLCTs in a BX from 10 to 5:
clctMinSeparation = cms.uint32(5),
# Debug
Expand All @@ -159,22 +170,24 @@
useDeadTimeZoning = cms.bool(True),

# Width (in #HS) of a fixed dead zone around a key HS:
clctStateMachineZone = cms.uint32(8),
clctStateMachineZone = cms.uint32(4),

# Enables the algo which instead of using the fixed dead zone width,
# varies it depending on the width of a triggered CLCT pattern
# (if True, the clctStateMachineZone is ignored):
useDynamicStateMachineZone = cms.bool(True),
useDynamicStateMachineZone = cms.bool(False),

# Pretrigger HS +- clctPretriggerTriggerZone sets the trigger matching zone
# which defines how far from pretrigger HS the TMB may look for a trigger HS
# (it becomes important to do so with localized dead-time zoning):
clctPretriggerTriggerZone = cms.uint32(5),
# not implemented yet, 2018-10-18, Tao
clctPretriggerTriggerZone = cms.uint32(224),

# whether to store the "corrected" CLCT stub time
# (currently it is median time of all hits in a pattern) into the CSCCLCTDigi bx,
# and temporary store the regular "key layer hit" time into the CSCCLCTDigi fullBX:
clctUseCorrectedBx = cms.bool(True)
# not feasible --Tao
clctUseCorrectedBx = cms.bool(False)
),

tmbParam = cms.PSet(
Expand Down Expand Up @@ -397,7 +410,7 @@
)

# to be used by ME31-ME41 chambers
me3141tmbSLHC = cms.PSet(
meX1tmbSLHC = cms.PSet(
mpcBlockMe1a = cms.uint32(0),
alctTrigEnable = cms.uint32(0),
clctTrigEnable = cms.uint32(0),
Expand All @@ -423,19 +436,21 @@
## unganging in ME1/a
from Configuration.Eras.Modifier_run2_common_cff import run2_common
run2_common.toModify( cscTriggerPrimitiveDigis,
debugParameters = True,
checkBadChambers = False,
commonParam = dict(gangedME1a = False)
)
debugParameters = True,
checkBadChambers = False,
commonParam = dict(gangedME1a = False),
)

## GEM-CSC ILT in ME1/1
from Configuration.Eras.Modifier_run3_GEM_cff import run3_GEM
run3_GEM.toModify( cscTriggerPrimitiveDigis,
GEMPadDigiProducer = cms.InputTag("simMuonGEMPadDigis"),
GEMPadDigiClusterProducer = cms.InputTag("simMuonGEMPadDigiClusters"),
commonParam = dict(isSLHC = True,
runME11Up = cms.bool(True),
runME11ILT = cms.bool(True),
useClusters = cms.bool(False)),
useClusters = cms.bool(False),
enableAlctSLHC = cms.bool(True)),
clctSLHC = dict(clctNplanesHitPattern = 3),
me11tmbSLHCGEM = me11tmbSLHCGEM,
copadParamGE11 = copadParamGE11
Expand All @@ -444,14 +459,18 @@
## GEM-CSC ILT in ME2/1, CSC in ME3/1 and ME4/1
from Configuration.Eras.Modifier_phase2_muon_cff import phase2_muon
phase2_muon.toModify( cscTriggerPrimitiveDigis,
commonParam = dict(runME21ILT = cms.bool(True),
runME3141ILT = cms.bool(True)),
commonParam = dict(runME21Up = cms.bool(True),
runME21ILT = cms.bool(True),
runME31Up = cms.bool(True),
runME41Up = cms.bool(True)),
tmbSLHC = dict(ignoreAlctCrossClct = cms.bool(True)),
clctSLHC = dict(useDynamicStateMachineZone = cms.bool(True)),
alctSLHCME21 = cscTriggerPrimitiveDigis.alctSLHC.clone(alctNplanesHitPattern = 3),
clctSLHCME21 = cscTriggerPrimitiveDigis.clctSLHC.clone(clctNplanesHitPattern = 3),
me21tmbSLHCGEM = me21tmbSLHCGEM,
alctSLHCME3141 = cscTriggerPrimitiveDigis.alctSLHC.clone(alctNplanesHitPattern = 4),
clctSLHCME3141 = cscTriggerPrimitiveDigis.clctSLHC.clone(clctNplanesHitPattern = 4),
me3141tmbSLHC = me3141tmbSLHC,
meX1tmbSLHC = meX1tmbSLHC,
copadParamGE11 = copadParamGE11,
copadParamGE21 = copadParamGE21
)
Loading