The final version of my custom 32-bit RISC CPU written in Verilog
Written for my Master's graduate project described here: http://connorgoldberg.com/projects/grad
Assembler is located here: https://github.com/connorjan/RISC-721-Assembler
More specific architecture information is described in the graduate paper with information also in the assembler user's guide here: https://assembler.connorgoldberg.com/