🔭 I'm currently working on RTL Deign (verilog, System Verilog, UVM)
👬 I'm looking to collaborate with people with same ideas of myself, developing projects on Verilog and VHDL
🌱 Im currently Gaining knowledge on Advanced digital design, Static timing analysis, Verilog HDL, FPGA architecture, CMOS fundamentals, Perl scripting, RISC V processor, ASIC verification methods, System verilog, Verification planning, Assertion based verification, Universal verification method and DFT.
💭 Ask/Talk to me about #RTLdesign #digitaldesign #socdesign #verification
✉️ How to reach me spamsofcp@gmail.com
⚡Fun Fact: The name "Verilog" is a portmanteau of the words "verification" and "logic". This is because Verilog is a hardware description language (HDL) that is used to describe digital systems at the register transfer level (RTL). RTL is the level of abstraction where data is transferred between registers, and Verilog is used to describe the logic that controls this data transfer! 🧮💻👩💼
HDLs : Verilog, VHDL
HVL : System Verilog
Languages : C language, Python, Perl
Tools : Xilinx Vivado, Mentor Graphics ModelSim, Siemens QuestaSim, Intel Quartus
Placement & Routing : Cadence Virtuoso
Verification : UVM, SystemVerilog Assertions, Formal Verification
Protocols : I2C, UART, RS232, SPI, AXI, APB, AMBA, DDR, PCIe
- Designing: Creating diverse digital hardware modules, ranging from simple components to more complex systems.
- Coding: Implementing RTL designs using languages like Verilog and VHDL, refining my coding skills along the way.
- Simulating: Verifying and testing the designs using simulation tools to ensure their correctness and functionality.
- Documenting: Sharing insights, challenges, and lessons learned daily, fostering a supportive learning community.
(currently working)
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