100 Days of RTL Design Journey

probable journey of RTL coding with Chandra Prakash

Welcome to the "100 Days of RTL Design Journey" repository! This is a personal challenge aimed at improving our RTL (Register Transfer Level) design skills and becoming proficient in digital hardware design. Throughout this journey, we will dedicate 100 consecutive days to learn, practice, and create RTL designs for various digital circuits.

I am Chandra Prakash, a VLSI enthusiast, and this is my journey of 100 days of RTL (Verilog, System Verilog, UVM). I mostly use Questasim software for the simulation of RTL codes, and the Synthesis is performed using Xilinx Vivado Design Suite.

Table of Contents

• Introduction
• Progress
• Resources
• Contribution

Introduction

RTL Design is a crucial aspect of digital hardware design, where we describe the behavior of digital circuits using hardware description languages (HDLs) like Verilog or VHDL. This repository is a personal commitment to dive deep into the world of RTL design, sharpen our skills, and become proficient in creating efficient and robust digital circuits.

Progress

Track our progress through the 100 days in this section. Below, you can find a table or list that will be regularly updated with the day number, design description, and links to each day's RTL design folder.

Verilog Implementations ---------------------------- System Verilog Implementations

Day	Design Description	Link	---	Day	Design Description	Link
1	Half Adder	Day 1		51	Reduction methods, Soring algos	Day 51
2	Full Adder	Day 2		52	Array manipulation methods	Day 52
3	Half Subtractor	Day 3		53	Interface concept	Day 53
4	3 bit ALU	Day 4		54	OOPS basics	Day 54
5	Binary to Gray converter	Day 5		55	Inheritance	Day 55
6	Multiplier	Day 6		56	Polymorphism	Day 56
7	BCD to Excess 3	Day 7		57	Shallow copy	Day 57
8	MUX Implementations	Day 8		58	Deep Copy	Day 58
9	DEMUX Implementations	Day 9		59	Randomization
10	Carry LookAhead Adder	Day 10		60
11	D- Flip Flop	Day 11		61
12	SR Flip Flop	Day 12		62
13	JK Flip Flop	Day 13		63
14	Master Slave Flip Flop	Day 14		64
15	SR latch	Day 15		65
16	Encoders & Decoders	Day 16		66
17	Counters	Day 17		67
18	Johnson Counter	Day 18		68
19	Ring Counter	Day 19		69
20	Up/Down Counter	Day 20		70
21	PISO Shift Register	Day 21		71
22	SIPO Shift Register	Day 22
23	Universal Shift Register	Day 23
24	Random-Access Memory	Day 34
25	Paralell Shifter	Day 25
26	Two port RAM	Day 26
27	Serial Adder	Day 27
28	FIFO queue Implementation	Day 28
29	LIFO queue Implementation	Day 29
30	Priority Encoder	Day 30
31	32 bit Ripple Carry Adder	Day 31
32	Sequence detector - Moore Model	Day 32
33	Priority Resolver	Day 33
34	Odd Frequency Generator	Day 34
35	Even Frequency generator	Day 35
36	Booth's Multiplier	Day 36
37	Pipeline Shiter	Day 37
38	Pseudo Random Frequency Generator	Day 38
39	Prime Number Finder	Day 39
40	Palindrome Checker	Day 40
41	32 Bit carry LookAhead Adder	Day 41
42	Butterfly Unit - DSP	Day 42
43	ROM design	Day 43
44	Fibonacci Generator	Day 44
45	Sequence detector using FSM	Day 45
46	Ceaser Cipher method	Day 46
47	Vending Machine	Day 47
48	Moore Model	Day 48
49	Cyclic redundancy code	Day 49
50	Hamming code generation	Day 50

Tools used

• Altera Model Sim (RTL and testbench simulation)
• Intel Quartus (Synthesis and Simulation)
• Xilinx Vivado ( Simulation, Testbench, Synthesis)

Resources

During this journey, we can refer to various resources to enhance our understanding and improve our RTL design skills. Here are some recommended resources:

• Book: "Digital Design with an introduction to Verilog HDL" by Morris mano and Michael D. Clietti
• Online Course: " System Design Through Verilog" by Prof. Shaik rafi Ahamed
• Other professional's referred Repos: Shashank Sirohiya | Kanna Akshay | Raul Behl

Contribution

Contributions to this repository are more than welcome! If you have suggestions, bug fixes, or want to add more RTL designs to the progress section, feel free to open an issue or submit a pull request.

License

This project is licensed under the BSD 3-Clause License - see the LICENSE file for details.

Usage

• Users are free to use, modify, and distribute this software in accordance with the terms of the license.
• Contributors must agree to the project's Contributor License Agreement (CLA) before submitting pull requests. Please refer to the Contributing user agreement file for more details.