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Improvement on cache invalidation #462
I've recently been fiddling with a multi threaded application using crossbeam channels. On threadripper I noticed that performance would degrade rapidly when the sender and receiver were on different CCX's (or in other words when cache wasn't shared between sender and receiver).
With a bit of digging I found that in the array implementation of channels does suffer from the buffer not being cach aligned.
I wrapped the buffer in a
I will keep this as a draft for now as while the benchmarks looks nice real world impact I measured is not as big as I hoped