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mmichaliINTCanguy11
mmichaliINTC
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ice: Implement PTP support for E830 devices
Add specific functions and definitions for E830 devices to enable PTP support. E830 devices support direct write to GLTSYN_ registers without shadow registers and 64 bit read of PHC time. Enable PTM for E830 device, which is required for cross timestamp and and dependency on PCIE_PTM for ICE_HWTS. Check X86_FEATURE_ART for E830 as it may not be present in the CPU. Cc: Anna-Maria Behnsen <anna-maria@linutronix.de> Cc: Frederic Weisbecker <frederic@kernel.org> Cc: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com> Co-developed-by: Jacob Keller <jacob.e.keller@intel.com> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Co-developed-by: Milena Olech <milena.olech@intel.com> Signed-off-by: Milena Olech <milena.olech@intel.com> Co-developed-by: Paul Greenwalt <paul.greenwalt@intel.com> Signed-off-by: Paul Greenwalt <paul.greenwalt@intel.com> Signed-off-by: Michal Michalik <michal.michalik@intel.com> Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com> Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Contingent worker at Intel) Signed-off-by: Tony Nguyen <anthony.l.nguyen@intel.com>
1 parent 381d577 commit f003075

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-7
lines changed

6 files changed

+262
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lines changed

‎drivers/net/ethernet/intel/Kconfig‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -336,7 +336,7 @@ config ICE_SWITCHDEV
336336
config ICE_HWTS
337337
bool "Support HW cross-timestamp on platforms with PTM support"
338338
default y
339-
depends on ICE && X86
339+
depends on ICE && X86 && PCIE_PTM
340340
help
341341
Say Y to enable hardware supported cross-timestamping on platforms
342342
with PCIe PTM support. The cross-timestamp is available through

‎drivers/net/ethernet/intel/ice/ice_hw_autogen.h‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -541,10 +541,22 @@
541541
#define PFPM_WUS_MAG_M BIT(1)
542542
#define PFPM_WUS_MNG_M BIT(3)
543543
#define PFPM_WUS_FW_RST_WK_M BIT(31)
544+
#define E830_PRTMAC_TS_TX_MEM_VALID_H 0x001E2020
545+
#define E830_PRTMAC_TS_TX_MEM_VALID_L 0x001E2000
544546
#define E830_PRTMAC_CL01_PS_QNT 0x001E32A0
545547
#define E830_PRTMAC_CL01_PS_QNT_CL0_M GENMASK(15, 0)
546548
#define E830_PRTMAC_CL01_QNT_THR 0x001E3320
547549
#define E830_PRTMAC_CL01_QNT_THR_CL0_M GENMASK(15, 0)
550+
#define E830_PRTTSYN_TXTIME_H(_i) (0x001E5800 + ((_i) * 32))
551+
#define E830_PRTTSYN_TXTIME_L(_i) (0x001E5000 + ((_i) * 32))
552+
#define E830_GLPTM_ART_CTL 0x00088B50
553+
#define E830_GLPTM_ART_CTL_ACTIVE_M BIT(0)
554+
#define E830_GLPTM_ART_TIME_H 0x00088B54
555+
#define E830_GLPTM_ART_TIME_L 0x00088B58
556+
#define E830_GLTSYN_PTMTIME_H(_i) (0x00088B48 + ((_i) * 4))
557+
#define E830_GLTSYN_PTMTIME_L(_i) (0x00088B40 + ((_i) * 4))
558+
#define E830_PFPTM_SEM 0x00088B00
559+
#define E830_PFPTM_SEM_BUSY_M BIT(0)
548560
#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4))
549561
#define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)
550562
#define E830_MBX_PF_IN_FLIGHT_VF_MSGS_THRESH 0x00234000

‎drivers/net/ethernet/intel/ice/ice_main.c‎

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4052,8 +4052,7 @@ static void ice_set_pf_caps(struct ice_pf *pf)
40524052
}
40534053

40544054
clear_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);
4055-
if (func_caps->common_cap.ieee_1588 &&
4056-
!(pf->hw.mac_type == ICE_MAC_E830))
4055+
if (func_caps->common_cap.ieee_1588)
40574056
set_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);
40584057

40594058
pf->max_pf_txqs = func_caps->common_cap.num_txq;
@@ -5073,6 +5072,12 @@ static int ice_init(struct ice_pf *pf)
50735072
if (err)
50745073
return err;
50755074

5075+
if (pf->hw.mac_type == ICE_MAC_E830) {
5076+
err = pci_enable_ptm(pf->pdev, NULL);
5077+
if (err)
5078+
dev_dbg(ice_pf_to_dev(pf), "PCIe PTM not supported by PCIe bus/controller\n");
5079+
}
5080+
50765081
err = ice_alloc_vsis(pf);
50775082
if (err)
50785083
goto err_alloc_vsis;

‎drivers/net/ethernet/intel/ice/ice_ptp.c‎

Lines changed: 70 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -310,6 +310,15 @@ ice_ptp_read_src_clk_reg(struct ice_pf *pf, struct ptp_system_timestamp *sts)
310310
/* Read the system timestamp pre PHC read */
311311
ptp_read_system_prets(sts);
312312

313+
if (hw->mac_type == ICE_MAC_E830) {
314+
u64 clk_time = rd64(hw, E830_GLTSYN_TIME_L(tmr_idx));
315+
316+
/* Read the system timestamp post PHC read */
317+
ptp_read_system_postts(sts);
318+
319+
return clk_time;
320+
}
321+
313322
lo = rd32(hw, GLTSYN_TIME_L(tmr_idx));
314323

315324
/* Read the system timestamp post PHC read */
@@ -1305,6 +1314,7 @@ ice_ptp_port_phy_stop(struct ice_ptp_port *ptp_port)
13051314

13061315
switch (hw->mac_type) {
13071316
case ICE_MAC_E810:
1317+
case ICE_MAC_E830:
13081318
err = 0;
13091319
break;
13101320
case ICE_MAC_GENERIC:
@@ -1351,6 +1361,7 @@ ice_ptp_port_phy_restart(struct ice_ptp_port *ptp_port)
13511361

13521362
switch (hw->mac_type) {
13531363
case ICE_MAC_E810:
1364+
case ICE_MAC_E830:
13541365
err = 0;
13551366
break;
13561367
case ICE_MAC_GENERIC:
@@ -1418,7 +1429,8 @@ void ice_ptp_link_change(struct ice_pf *pf, bool linkup)
14181429

14191430
switch (hw->mac_type) {
14201431
case ICE_MAC_E810:
1421-
/* Do not reconfigure E810 PHY */
1432+
case ICE_MAC_E830:
1433+
/* Do not reconfigure E810 or E830 PHY */
14221434
return;
14231435
case ICE_MAC_GENERIC:
14241436
case ICE_MAC_GENERIC_3K_E825:
@@ -1451,6 +1463,7 @@ static int ice_ptp_cfg_phy_interrupt(struct ice_pf *pf, bool ena, u32 threshold)
14511463

14521464
switch (hw->mac_type) {
14531465
case ICE_MAC_E810:
1466+
case ICE_MAC_E830:
14541467
return 0;
14551468
case ICE_MAC_GENERIC: {
14561469
int quad;
@@ -2202,6 +2215,21 @@ static const struct ice_crosststamp_cfg ice_crosststamp_cfg_e82x = {
22022215
.dev_time_h[1] = GLTSYN_HHTIME_H(1),
22032216
};
22042217

2218+
#ifdef CONFIG_ICE_HWTS
2219+
static const struct ice_crosststamp_cfg ice_crosststamp_cfg_e830 = {
2220+
.lock_reg = E830_PFPTM_SEM,
2221+
.lock_busy = E830_PFPTM_SEM_BUSY_M,
2222+
.ctl_reg = E830_GLPTM_ART_CTL,
2223+
.ctl_active = E830_GLPTM_ART_CTL_ACTIVE_M,
2224+
.art_time_l = E830_GLPTM_ART_TIME_L,
2225+
.art_time_h = E830_GLPTM_ART_TIME_H,
2226+
.dev_time_l[0] = E830_GLTSYN_PTMTIME_L(0),
2227+
.dev_time_h[0] = E830_GLTSYN_PTMTIME_H(0),
2228+
.dev_time_l[1] = E830_GLTSYN_PTMTIME_L(1),
2229+
.dev_time_h[1] = E830_GLTSYN_PTMTIME_H(1),
2230+
};
2231+
2232+
#endif /* CONFIG_ICE_HWTS */
22052233
/**
22062234
* struct ice_crosststamp_ctx - Device cross timestamp context
22072235
* @snapshot: snapshot of system clocks for historic interpolation
@@ -2323,6 +2351,11 @@ static int ice_ptp_getcrosststamp(struct ptp_clock_info *info,
23232351
case ICE_MAC_GENERIC_3K_E825:
23242352
ctx.cfg = &ice_crosststamp_cfg_e82x;
23252353
break;
2354+
#ifdef CONFIG_ICE_HWTS
2355+
case ICE_MAC_E830:
2356+
ctx.cfg = &ice_crosststamp_cfg_e830;
2357+
break;
2358+
#endif /* CONFIG_ICE_HWTS */
23262359
default:
23272360
return -EOPNOTSUPP;
23282361
}
@@ -2658,6 +2691,28 @@ static void ice_ptp_set_funcs_e810(struct ice_pf *pf)
26582691
}
26592692
}
26602693

2694+
/**
2695+
* ice_ptp_set_funcs_e830 - Set specialized functions for E830 support
2696+
* @pf: Board private structure
2697+
*
2698+
* Assign functions to the PTP capabiltiies structure for E830 devices.
2699+
* Functions which operate across all device families should be set directly
2700+
* in ice_ptp_set_caps. Only add functions here which are distinct for E830
2701+
* devices.
2702+
*/
2703+
static void ice_ptp_set_funcs_e830(struct ice_pf *pf)
2704+
{
2705+
#ifdef CONFIG_ICE_HWTS
2706+
if (pcie_ptm_enabled(pf->pdev) && boot_cpu_has(X86_FEATURE_ART))
2707+
pf->ptp.info.getcrosststamp = ice_ptp_getcrosststamp;
2708+
2709+
#endif /* CONFIG_ICE_HWTS */
2710+
/* Rest of the config is the same as base E810 */
2711+
pf->ptp.ice_pin_desc = ice_pin_desc_e810;
2712+
pf->ptp.info.n_pins = ICE_PIN_DESC_ARR_LEN(ice_pin_desc_e810);
2713+
ice_ptp_setup_pin_cfg(pf);
2714+
}
2715+
26612716
/**
26622717
* ice_ptp_set_caps - Set PTP capabilities
26632718
* @pf: Board private structure
@@ -2684,6 +2739,9 @@ static void ice_ptp_set_caps(struct ice_pf *pf)
26842739
case ICE_MAC_E810:
26852740
ice_ptp_set_funcs_e810(pf);
26862741
return;
2742+
case ICE_MAC_E830:
2743+
ice_ptp_set_funcs_e830(pf);
2744+
return;
26872745
case ICE_MAC_GENERIC:
26882746
case ICE_MAC_GENERIC_3K_E825:
26892747
ice_ptp_set_funcs_e82x(pf);
@@ -2844,6 +2902,16 @@ irqreturn_t ice_ptp_ts_irq(struct ice_pf *pf)
28442902

28452903
set_bit(ICE_MISC_THREAD_TX_TSTAMP, pf->misc_thread);
28462904
return IRQ_WAKE_THREAD;
2905+
case ICE_MAC_E830:
2906+
/* E830 can read timestamps in the top half using rd32() */
2907+
if (ice_ptp_process_ts(pf) == ICE_TX_TSTAMP_WORK_PENDING) {
2908+
/* Process outstanding Tx timestamps. If there
2909+
* is more work, re-arm the interrupt to trigger again.
2910+
*/
2911+
wr32(hw, PFINT_OICR, PFINT_OICR_TSYN_TX_M);
2912+
ice_flush(hw);
2913+
}
2914+
return IRQ_HANDLED;
28472915
default:
28482916
return IRQ_HANDLED;
28492917
}
@@ -3229,6 +3297,7 @@ static int ice_ptp_init_port(struct ice_pf *pf, struct ice_ptp_port *ptp_port)
32293297

32303298
switch (hw->mac_type) {
32313299
case ICE_MAC_E810:
3300+
case ICE_MAC_E830:
32323301
case ICE_MAC_GENERIC_3K_E825:
32333302
return ice_ptp_init_tx(pf, &ptp_port->tx, ptp_port->port_num);
32343303
case ICE_MAC_GENERIC:

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