Stall does not stall PC stage (at least in a core view)

[ppisa]

.text

_start:
loop:
	addi x1, x0, 0x11
	addi x2, x0, 0x22
	addi x3, x0, 0x33
	lw   x4, 0x44(x0)
	addi x5, x4, 0x55
	beq  x0, x0, tgt1
	addi x11, x0, 0x11
	addi x12, x0, 0x22
	addi x13, x0, 0x33
	addi x14, x0, 0x44
	addi x15, x0, 0x55
tgt1:
	addi x21, x0, 0x11
	addi x22, x0, 0x22
	addi x23, x0, 0x33
	addi x24, x0, 0x44
	addi x25, x0, 0x55

	ebreak

[ppisa]

Thanks for updates. I have doubts if to remove IMF_STOP_IF, because barrier instructions would require something like that one day. May it be even syscall and some other instructions... On the other hand, it can be reintroduced when required again and adjusted for actual needs.

The state is much better then before but there are still some problems in visualization.

[jdupak]

The regwrite box in mem is IMO correct as NOP is ADDI x0, x0, 0.

[ppisa]

Hmm, I am in the doubt there, I would prefer if the flush sets all signals into inactive state and because signal should go as independent signal through stages then it should be assigned by flush already anyway so I would left it inactive in the stall bubble.

[jdupak]

I have pushed a fix of the misconnected labels.

Hmm, I am in the doubt there, I would prefer if the flush sets all signals into inactive state and because signal should go as independent signal through stages then it should be assigned by flush already anyway so I would left it inactive in the stall bubble.

I dislike the idea, that I say, that the stage processes a NOP (which is ADDI), but the bubbles would behave differently for explicit NOP and stall caused NOP (and for the initial state of the pipeline as well).

[ppisa]

The other option is to set RegWrite to 0 even for these instructions which write to reg x0. May it be it even can simplify some expression in forwarding.