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Add Yosys linter for Verilog files. #3713

Merged
merged 8 commits into from
Jul 12, 2021
Merged

Add Yosys linter for Verilog files. #3713

merged 8 commits into from
Jul 12, 2021

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nwsharp
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@nwsharp nwsharp commented May 3, 2021

This changeset adds the Yosys linter for Verilog files. I have no association with the Yosys project, besides being a happy user!

http://www.clifford.at/yosys/
https://github.com/YosysHQ/yosys

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nwsharp commented May 12, 2021

Is there anything needed from me to move this PR along?

@hsanson hsanson closed this Jul 9, 2021
@hsanson hsanson reopened this Jul 9, 2021
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nwsharp commented Jul 11, 2021

@hsanson Looks like we're good to go again. Previous CI failure was because this branch was no longer up-to-date with master since it's been so long.

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Thanks

@hsanson hsanson merged commit c8f6692 into dense-analysis:master Jul 12, 2021
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