This project is a C++ superscalar processor simulator that reads in a text file describing a trace of instructions of the format:

21fc80 2 4 16 -1
21fc84 0 -1 4 0
21fc8c 2 2 28 -1
21fc90 2 3 16 -1
21fc94 0 -1 16 2
21fc98 0 -1 3 0
21fcc0 0 2 16 -1
21fcc4 0 2 2 -1
etc...

Where the generic format is: [address] [instruction type] [destination register] [source register 1] [source register 2].
Register values of -1 indicate the absence of a register.

For the purposes of simulation, instruction type describes the number of cycles a given instruction would take during the execution stage EX.

The nine stages are as follows:
FE - Fetch
DE - Decode
RN - Rename
RR - Register Read
DI - Dispatch (to Issue Queue)
IS - Issue (from Issue Queue to execution)
EX - Execute
WB - Writeback
RT - Retire.

The final result of the engine outputs statistics on how many cycles the pipeline takes to execute, as well as instructions per cycle.

Input parameters may vary superscalar width (a width of 1 makes the processor scalar), size of the ReOrder Buffer (ROB), and size of the Issue Queue (IQ).

NOTE: This program utilizes different terminology for the stages than that found in Hennessy & Patterson. The user is cautioned of this to avoid confusion.