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OMRTreeEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
//On zOS XLC linker can't handle files with same name at link time
//This workaround with pragma is needed. What this does is essentially
//give a different name to the codesection (csect) for this file. So it
//doesn't conflict with another file with same name.
#pragma csect(CODE,"TRZTreeEvalBase#C")
#pragma csect(STATIC,"TRZTreeEvalBase#S")
#pragma csect(TEST,"TRZTreeEvalBase#T")
#include <ctype.h>
#include <math.h>
#include <stddef.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include "codegen/CodeGenerator.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LinkageConventionsEnum.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/Snippet.hpp"
#include "codegen/StorageInfo.hpp"
#include "codegen/SystemLinkage.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "codegen/S390Evaluator.hpp"
#include "codegen/UnresolvedDataSnippet.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/ObjectModel.hpp"
#include "env/PersistentInfo.hpp"
#include "env/StackMemoryRegion.hpp"
#include "env/TRMemory.hpp"
#include "env/defines.h"
#include "env/jittypes.h"
#include "il/AutomaticSymbol.hpp"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ParameterSymbol.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/StaticSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Array.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/BitVector.hpp"
#include "infra/HashTab.hpp"
#include "infra/List.hpp"
#include "infra/Random.hpp"
#include "infra/CfgEdge.hpp"
#include "infra/CfgNode.hpp"
#include "optimizer/OptimizationManager.hpp"
#include "optimizer/Optimizations.hpp"
#include "optimizer/Optimizer.hpp"
#include "optimizer/TransformUtil.hpp"
#include "ras/Debug.hpp"
#include "ras/DebugCounter.hpp"
#include "runtime/Runtime.hpp"
#include "z/codegen/BinaryCommutativeAnalyser.hpp"
#include "z/codegen/OpMemToMem.hpp"
#include "z/codegen/S390GenerateInstructions.hpp"
#include "z/codegen/S390HelperCallSnippet.hpp"
#include "z/codegen/S390Instruction.hpp"
#include "z/codegen/S390OutOfLineCodeSection.hpp"
#ifdef J9_PROJECT_SPECIFIC
#include "z/codegen/S390Register.hpp"
#endif
#ifdef J9_PROJECT_SPECIFIC
TR::Instruction *
generateS390PackedCompareAndBranchOps(TR::Node * node,
TR::CodeGenerator * cg,
TR::InstOpCode::S390BranchCondition fBranchOpCond,
TR::InstOpCode::S390BranchCondition rBranchOpCond,
TR::InstOpCode::S390BranchCondition &retBranchOpCond,
TR::LabelSymbol *branchTarget = NULL);
#endif
TR::Instruction*
generateLoad32BitConstant(TR::CodeGenerator* cg, TR::Node* node, int32_t value, TR::Register* targetRegister, bool canSetConditionCode, TR::Instruction* cursor, TR::RegisterDependencyConditions* dependencies, TR::Register* literalPoolRegister)
{
TR::Symbol *sym = NULL;
if (node->getOpCode().hasSymbolReference())
sym = node->getSymbol();
bool load64bit = node->getType().isInt64() || node->isExtendedTo64BitAtSource();
if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
{
if (load64bit)
{
return generateRIInstruction(cg, TR::InstOpCode::LGHI, node, targetRegister, value, cursor);
}
else
{
// Prefer to generate XR over LHI if possible to save 2 bytes of icache
if (value == 0 && canSetConditionCode && !cg->getConditionalMovesEvaluationMode())
{
return generateRRInstruction(cg, TR::InstOpCode::XR, node, targetRegister, targetRegister, cursor);
}
else
{
return generateRIInstruction(cg, TR::InstOpCode::LHI, node, targetRegister, value, cursor);
}
}
}
else if (load64bit && value >= 0 && value <= 65535)
{
// Zero-extended halfword
return generateRIInstruction(cg, TR::InstOpCode::LLILL, node, targetRegister, value, cursor);
}
else
{
if (sym)
{
if (cg->comp()->compileRelocatableCode() && sym->isDebugCounter())
return generateRegLitRefInstruction(cg, TR::InstOpCode::L, node, targetRegister, value, TR_DebugCounter, dependencies, cursor, literalPoolRegister);
if (sym->isStatic() && !sym->isClassObject() && !sym->isNotDataAddress())
return generateRegLitRefInstruction(cg, TR::InstOpCode::L, node, targetRegister, value, TR_DataAddress, dependencies, cursor, literalPoolRegister);
if (sym->isCountForRecompile())
return generateRegLitRefInstruction(cg, TR::InstOpCode::L, node, targetRegister, value, TR_GlobalValue, dependencies, cursor, literalPoolRegister);
if (sym->isRecompilationCounter())
return generateRegLitRefInstruction(cg, TR::InstOpCode::L, node, targetRegister, value, TR_BodyInfoAddress, dependencies, cursor, literalPoolRegister);
if (cg->needRelocationsForPersistentProfileInfoData() && sym->isBlockFrequency())
return generateRegLitRefInstruction(cg, TR::InstOpCode::L, node, targetRegister, value, TR_BlockFrequency, dependencies, cursor, literalPoolRegister);
if (cg->needRelocationsForPersistentProfileInfoData() && sym->isRecompQueuedFlag())
return generateRegLitRefInstruction(cg, TR::InstOpCode::L, node, targetRegister, value, TR_RecompQueuedFlag, dependencies, cursor, literalPoolRegister);
}
}
if (load64bit)
{
// Sign-extended 32-bit
return generateRILInstruction(cg, TR::InstOpCode::LGFI, node, targetRegister, value, cursor);
}
else
{
return generateRILInstruction(cg, TR::InstOpCode::IILF, node, targetRegister, value, cursor);
}
}
/**
* Generate code to load a long constant
*/
TR::Instruction *
genLoadLongConstant(TR::CodeGenerator * cg, TR::Node * node, int64_t value, TR::Register * targetRegister, TR::Instruction * cursor,
TR::RegisterDependencyConditions * cond, TR::Register * base)
{
TR::Compilation *comp = cg->comp();
TR::Symbol *sym = NULL;
if (node->getOpCode().hasSymbolReference())
sym = node->getSymbol();
if (cg->comp()->compileRelocatableCode() && sym && sym->isDebugCounter())
{
cursor = generateRegLitRefInstruction(cg, TR::InstOpCode::LG, node, targetRegister, value, TR_DebugCounter, cond, cursor, base);
}
else if (cg->needRelocationsForPersistentInfoData() && sym && (sym->isCountForRecompile()))
{
TR::Instruction * temp = cursor;
cursor = generateRegLitRefInstruction(cg, TR::InstOpCode::LG, node, targetRegister, value, TR_GlobalValue, cond, cursor, base);
}
else if (cg->needRelocationsForBodyInfoData() && sym && sym->isRecompilationCounter())
{
TR::Instruction * temp = cursor;
cursor = generateRegLitRefInstruction(cg, TR::InstOpCode::LG, node, targetRegister, value, TR_BodyInfoAddress, cond, cursor, base);
}
else if (cg->needRelocationsForStatics() && sym && sym->isStatic() && !sym->isClassObject() && !sym->isNotDataAddress())
{
TR::Instruction * temp = cursor;
cursor = generateRegLitRefInstruction(cg, TR::InstOpCode::LG, node, targetRegister, value, TR_DataAddress, cond, cursor, base);
}
else if (cg->needRelocationsForPersistentProfileInfoData() && sym && sym->isBlockFrequency())
{
cursor = generateRegLitRefInstruction(cg, TR::InstOpCode::LG, node, targetRegister, value, TR_BlockFrequency, cond, cursor, base);
}
else if (cg->needRelocationsForPersistentProfileInfoData() && sym && sym->isRecompQueuedFlag())
{
cursor = generateRegLitRefInstruction(cg, TR::InstOpCode::LG, node, targetRegister, value, TR_RecompQueuedFlag, cond, cursor, base);
}
else if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL && !comp->compileRelocatableCode())
{
cursor = generateRIInstruction(cg, TR::InstOpCode::LGHI, node, targetRegister, value, cursor);
}
else if (value >= GE_MIN_IMMEDIATE_VAL && value <= GE_MAX_IMMEDIATE_VAL) // value is signed 32bit - use sign extension
{
// If within Golden Eagle min and max immediate value, then use Load immediate.
cursor = generateRILInstruction(cg, TR::InstOpCode::LGFI, node, targetRegister, static_cast<int32_t>(value), cursor);
}
else if (!(value & CONSTANT64(0x00000000FFFFFFFF)))
{
// Value is of 0x********00000000, we can use Golden Eagle LLIHF instr to load
// the high 32 bits
int32_t value32 = value >> 32;
cursor = generateRILInstruction(cg, TR::InstOpCode::LLIHF, node, targetRegister, value32, cursor);
}
else if (!(value & CONSTANT64(0xFFFFFFFF00000000))) // 2^33 < value <= 2^32 ; value is unsigned 32bit so use load logical
{
cursor = generateRILInstruction(cg, TR::InstOpCode::LLILF, node, targetRegister, static_cast<int32_t>(value), cursor);
}
//disable LARL for AOT for easier relocation
//cannot safely generate LARL for longs on 31-bit
else if (cg->canUseRelativeLongInstructions(value) &&
comp->target().is64Bit() && !comp->compileRelocatableCode())
{
cursor = generateRILInstruction(cg, TR::InstOpCode::LARL, node, targetRegister, reinterpret_cast<void*>(value), cursor);
}
else
{
int32_t high32 = value >> 32;
cursor = generateRILInstruction(cg, TR::InstOpCode::LLIHF, node, targetRegister, high32, cursor);
cursor = generateRILInstruction(cg, TR::InstOpCode::IILF, node, targetRegister, static_cast<int32_t>(value), cursor);
}
return cursor;
}
/**
* Generate code to load an address constant
*/
TR::Instruction *
genLoadAddressConstant(TR::CodeGenerator * cg, TR::Node * node, uintptr_t value, TR::Register * targetRegister,
TR::Instruction * cursor, TR::RegisterDependencyConditions * cond, TR::Register * base)
{
if (cg->profiledPointersRequireRelocation() &&
node->getOpCodeValue() == TR::aconst &&
(node->isMethodPointerConstant() || node->isClassPointerConstant()))
{
TR_ExternalRelocationTargetKind reloKind = TR_NoRelocation;
if (node->isMethodPointerConstant())
{
reloKind = TR_MethodPointer;
if (node->getInlinedSiteIndex() == -1)
reloKind = TR_RamMethod;
}
else if (node->isClassPointerConstant())
reloKind = TR_ClassPointer;
TR_ASSERT(reloKind != TR_NoRelocation, "relocation kind shouldn't be TR_NoRelocation");
return generateRegLitRefInstruction(cg, TR::InstOpCode::getLoadOpCode(), node, targetRegister, (uintptr_t) value, reloKind, cond, cursor, base);
}
TR::Symbol *symbol = NULL;
TR::Compilation *comp = cg->comp();
if (node && node->getOpCode().hasSymbolReference())
symbol = node->getSymbol();
bool isPICCandidate = symbol ? symbol->isStatic() && symbol->isClassObject() : false;
if (isPICCandidate && !cg->comp()->compileRelocatableCode()
&& cg->wantToPatchClassPointer((TR_OpaqueClassBlock*)value, node))
return genLoadAddressConstantInSnippet(cg, node, (uintptr_t)value, targetRegister, cursor, cond, base, true);
if (node->isClassUnloadingConst())
{
uintptr_t value = node->getAddress();
TR::Instruction *unloadableConstInstr = NULL;
if (cg->canUseRelativeLongInstructions(value))
{
unloadableConstInstr = generateRILInstruction(cg, TR::InstOpCode::LARL, node, targetRegister, reinterpret_cast<void*>(value));
}
else
{
unloadableConstInstr = genLoadAddressConstantInSnippet(cg, node, value, targetRegister, NULL, NULL, NULL, true);
}
if (node->isMethodPointerConstant())
{
comp->getStaticMethodPICSites()->push_front(unloadableConstInstr);
}
else
{
comp->getStaticPICSites()->push_front(unloadableConstInstr);
}
return unloadableConstInstr;
}
if (cg->comp()->target().is64Bit())
{
return genLoadLongConstant(cg, node, (uint64_t) value, targetRegister, cursor, cond, base);
}
else
{
// TODO: We should update this API as well to accept a "canSetConditionCode" and forward that argument here rather than passing false blindly.
return generateLoad32BitConstant(cg, node, (int32_t) value, targetRegister, false, cursor, cond, base);
}
}
TR::Instruction *
genLoadAddressConstantInSnippet(TR::CodeGenerator * cg, TR::Node * node, uintptr_t value, TR::Register * targetRegister,
TR::Instruction * cursor, TR::RegisterDependencyConditions * cond, TR::Register * base, bool isPICCandidate)
{
return generateRegLitRefInstruction(cg, TR::InstOpCode::getLoadOpCode(), node, targetRegister, value, cond, NULL, base, isPICCandidate);
}
static TR::Register *
generateLoad32BitConstant(TR::CodeGenerator * cg, TR::Node * constExpr)
{
TR::Register * tempReg = NULL;
switch (constExpr->getDataType())
{
case TR::Int8:
tempReg = cg->allocateRegister();
generateLoad32BitConstant(cg, constExpr, constExpr->getByte(), tempReg, false);
break;
case TR::Int16:
tempReg = cg->allocateRegister();
generateLoad32BitConstant(cg, constExpr, constExpr->getShortInt(), tempReg, false);
break;
case TR::Int32:
tempReg = cg->allocateRegister();
generateLoad32BitConstant(cg, constExpr, constExpr->getInt(), tempReg, false);
break;
case TR::Address:
tempReg = cg->allocateRegister();
if (cg->comp()->target().is64Bit())
{
genLoadLongConstant(cg, constExpr, constExpr->getLongInt(), tempReg);
}
else
{
generateLoad32BitConstant(cg, constExpr, constExpr->getInt(), tempReg, false);
}
break;
case TR::Int64:
{
tempReg = cg->allocateRegister();
genLoadLongConstant(cg, constExpr, constExpr->getLongInt(), tempReg);
break;
}
case TR::Float:
tempReg = cg->allocateRegister(TR_FPR);
generateRegLitRefInstruction(cg, TR::InstOpCode::LE, constExpr, tempReg, constExpr->getFloat());
break;
case TR::Double:
tempReg = cg->allocateRegister(TR_FPR);
generateRegLitRefInstruction(cg, TR::InstOpCode::LD, constExpr, tempReg, constExpr->getDouble());
break;
default:
TR_ASSERT( 0, "Unexpected datatype encountered on genLoad");
break;
}
return tempReg;
}
int64_t
getIntegralValue(TR::Node * node)
{
int64_t value = 0;
if (node->getOpCode().isLoadConst())
{
switch (node->getDataType())
{
case TR::Int8:
value = node->getByte();
break;
case TR::Int16:
value = node->getShortInt();
break;
case TR::Int32:
value = node->getInt();
break;
case TR::Address:
value = node->getAddress();
break;
case TR::Int64:
value = node->getLongInt();
break;
default:
TR_ASSERT(0, "Unexpected element load datatype encountered");
break;
}
}
return value;
}
TR::Instruction *multiply31Reduction(TR::CodeGenerator * cg, TR::Node * node,
TR::Register * sourceRegister, TR::Register * targetRegister, int32_t value,
TR::Instruction * preced = NULL)
{
TR::Compilation *comp = cg->comp();
TR::Instruction * cursor = NULL;
int32_t absValue = (value < 0) ? -value : value;
int32_t shiftValue = TR::TreeEvaluator::checkNonNegativePowerOfTwo(absValue);
if (value == -1)
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LCR, node, targetRegister, sourceRegister, preced);
return cursor;
}
if (shiftValue >= 0 && shiftValue < 32)
{
int32_t numOperations = 0;
if (shiftValue != 0)
{
numOperations += 1;
}
if (value < 0)
{
numOperations += 1;
}
if (!cg->mulDecompositionCostIsJustified(numOperations, 0, 0, (int64_t)value))
{
return NULL;
}
if (shiftValue != 0)
{
if (targetRegister != sourceRegister)
{
if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_S390_Z196))
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLLK, node, targetRegister, sourceRegister, shiftValue, preced);
}
else
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLLG, node, targetRegister, sourceRegister, shiftValue, preced);
}
}
else
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLL, node, targetRegister, shiftValue, preced);
}
}
if (value < 0)
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LCR, node, targetRegister, targetRegister, (cursor != NULL) ? cursor : preced);
}
return cursor;
}
// find bracketing powers of 2 and use this to see if an easy shift/add or shift/subtract
// sequence can be done. also - optimize for the case where it is (2**i -1) or (2**i + 1)
// since this can be done more efficiently (the shift degrades into a no-op since it is a shift
// of 0
int32_t before = 31;
for (int32_t i = 1; i < 32; i++)
{
if (0x1 << i > absValue)
{
before = i - 1; break;
}
}
int32_t after = before + 1;
int32_t posDifference = absValue - (1 << before);
int32_t negDifference = (int32_t) ((((int64_t) 1) << after) - absValue);
shiftValue = TR::TreeEvaluator::checkNonNegativePowerOfTwo(posDifference); // i.e. 3, 5, 9, 17, 6, 10, 18, 20
if (shiftValue >= 0 && shiftValue < 32)
{
int32_t numOperations =
((sourceRegister != targetRegister) ? 1 : 0) + // first LR
1 + // second LR
((before != 0) ? 1 : 0) + // first SLL
((shiftValue != 0) ? 1 : 0) + // second SLL
1 + // AR
((value < 0) ? 1 : 0); // LCR
if (!cg->mulDecompositionCostIsJustified(numOperations, 0, 0, (int64_t)value))
{
return NULL;
}
TR::Register * tempRegister = cg->allocateRegister();
if (sourceRegister != targetRegister)
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LR, node, targetRegister, sourceRegister, preced);
}
cursor = generateRRInstruction(cg, TR::InstOpCode::LR, node, tempRegister, sourceRegister, (cursor != NULL) ? cursor : preced);
if (before != 0)
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLL, node, targetRegister, before, cursor);
}
if (shiftValue != 0)
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLL, node, tempRegister, shiftValue, cursor);
}
cursor = generateRRInstruction(cg, TR::InstOpCode::AR, node, targetRegister, tempRegister, cursor);
if (value < 0)
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LCR, node, targetRegister, targetRegister);
}
cg->stopUsingRegister(tempRegister);
return cursor;
}
shiftValue = TR::TreeEvaluator::checkNonNegativePowerOfTwo(negDifference); // i.e. 7, 12, 14, 15,
if (shiftValue >= 0 && shiftValue < 32)
{
int32_t numOperations =
((sourceRegister != targetRegister) ? 1 : 0) + // first LR
1 + // second LR
((after != 0) ? 1 : 0) + // first SLL
((shiftValue != 0) ? 1 : 0) + // second SLL
1 + // SR
((value < 0) ? 1 : 0); // LCR
if (!cg->mulDecompositionCostIsJustified(numOperations, 0, 0, (int64_t)value))
{
return NULL;
}
TR::Register * tempRegister = cg->allocateRegister();
if (targetRegister != sourceRegister)
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LR, node, targetRegister, sourceRegister, preced);
}
cursor = generateRRInstruction(cg, TR::InstOpCode::LR, node, tempRegister, sourceRegister, (cursor != NULL) ? cursor : preced);
if (after != 0)
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLL, node, targetRegister, after, cursor);
}
if (shiftValue != 0)
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLL, node, tempRegister, shiftValue, cursor);
}
cursor = generateRRInstruction(cg, TR::InstOpCode::SR, node, targetRegister, tempRegister, cursor);
if (value < 0)
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LCR, node, targetRegister, targetRegister, cursor);
}
cg->stopUsingRegister(tempRegister);
return cursor;
}
return NULL;
}
/**
* Reduce multiply High when the value is power of 2 in 64-bit.
* This function returns the high word of the multiplication result.
*/
TR::Instruction *multiplyHigh64Reduction(TR::CodeGenerator * cg, TR::Node * node,
TR::Register * sourceRegister, TR::Register * targetRegister, int64_t value)
{
TR::Instruction * cursor = NULL;
int64_t absValue = (value < 0) ? -value : value;
int64_t shiftValue = TR::TreeEvaluator::checkNonNegativePowerOfTwo(absValue);
if (shiftValue >=0 && shiftValue < 64)
{
// Shift left by 'shiftValue' amount == shift right by 64-shiftValue
cursor = generateRSInstruction(cg, TR::InstOpCode::SRLG, node, targetRegister, sourceRegister, 64-shiftValue);
return cursor;
}
return NULL;
}
TR::Instruction *multiply64Reduction(TR::CodeGenerator * cg, TR::Node * node,
TR::Register * sourceRegister, TR::Register * targetRegister, int64_t value, TR::Instruction * preced = NULL)
{
TR::Instruction * cursor = NULL;
int64_t absValue = (value < 0) ? -value : value;
int64_t shiftValue = TR::TreeEvaluator::checkNonNegativePowerOfTwo(absValue);
if (value == -1)
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LCGR, node, targetRegister, sourceRegister, preced);
return cursor;
}
if (shiftValue >= 0 && shiftValue < 64)
{
int32_t numOperations =
((shiftValue != 0) ? 1 : 0) + // SLLG
((value < 0) ? 1 : 0); // LCGR
if (!cg->mulDecompositionCostIsJustified(numOperations, 0, 0, value))
{
return NULL;
}
if (shiftValue != 0)
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLLG, node, targetRegister, sourceRegister, shiftValue, preced);
}
if (value < 0)
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LCGR, node, targetRegister, targetRegister,
(cursor != NULL) ? cursor : preced);
}
return cursor;
}
// find bracketing powers of 2 and use this to see if an easy shift/add or shift/subtract
// sequence can be done. also - optimize for the case where it is (2**i -1) or (2**i + 1)
// since this can be done more efficiently (the shift degrades into a no-op since it is a shift
// of 0. 1st and 2nd orders of Booth's algorithm
int32_t before = 63;
for (int32_t i = 1; i < 64; i++)
{
if (0x1 << i > absValue)
{
before = i - 1; break;
}
}
int32_t after = before + 1;
int64_t posDifference = absValue - (1 << before);
int64_t negDifference = ((((int64_t) 1) << after) - absValue);
shiftValue = TR::TreeEvaluator::checkNonNegativePowerOfTwo(posDifference); // i.e. 3, 5, 9, 17, 6, 10, 18, 20
if (shiftValue >= 0 && shiftValue < 64)
{
int32_t numOperations =
1 + // LGR
((shiftValue != 0) ? 1 : 0) + // first SLLG
((before != 0) ? 1 : 0) + // second SLLG
1 + // AGR
((value < 0) ? 1 : 0); // LCGR
if (!cg->mulDecompositionCostIsJustified(numOperations, 0, 0, value))
{
return NULL;
}
TR::Register * tempRegister = cg->allocateRegister();
cursor = generateRRInstruction(cg, TR::InstOpCode::LGR, node, tempRegister, sourceRegister, preced);
if (shiftValue != 0)
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLLG, node, tempRegister, sourceRegister, shiftValue, cursor);
}
if (before != 0)
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLLG, node, targetRegister, sourceRegister, before, cursor);
}
cursor = generateRRInstruction(cg, TR::InstOpCode::AGR, node, targetRegister, tempRegister, cursor);
if (value < 0)
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LCGR, node, targetRegister, targetRegister, cursor);
}
cg->stopUsingRegister(tempRegister);
return cursor;
}
shiftValue = TR::TreeEvaluator::checkNonNegativePowerOfTwo(negDifference); // i.e. 7, 12, 14, 15,
if (shiftValue >= 0 && shiftValue < 64)
{
int32_t numOperations =
1 + // LGR
((shiftValue != 0) ? 1 : 0) + // first SLLG
((after != 0) ? 1 : 0) + // second SLLG
1 + // SGR
((value < 0) ? 1 : 0); // LCGR
if (!cg->mulDecompositionCostIsJustified(numOperations, 0, 0, value))
{
return NULL;
}
TR::Register * tempRegister = cg->allocateRegister();
cursor = generateRRInstruction(cg, TR::InstOpCode::LGR, node, tempRegister, sourceRegister, preced);
if (shiftValue != 0)
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLLG, node, tempRegister, sourceRegister, shiftValue, cursor);
}
if (after != 0)
{
cursor = generateRSInstruction(cg, TR::InstOpCode::SLLG, node, targetRegister, sourceRegister, after, cursor);
}
cursor = generateRRInstruction(cg, TR::InstOpCode::SGR, node, targetRegister, tempRegister, cursor);
if (value < 0)
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LCGR, node, targetRegister, targetRegister, cursor);
}
cg->stopUsingRegister(tempRegister);
return cursor;
}
return NULL;
}
TR::Instruction *
generateS390ImmOp(TR::CodeGenerator * cg, TR::InstOpCode::Mnemonic memOp, TR::Node * node,
TR::Register * sourceRegister, TR::Register * targetRegister, int32_t value, TR::RegisterDependencyConditions * cond,
TR::Register * base, TR::Instruction * preced)
{
TR::Compilation *comp = cg->comp();
TR::Instruction * cursor = NULL, *resultMultReduction = NULL;
TR::InstOpCode::Mnemonic immOp = TR::InstOpCode::BAD;
// LL: Store Golden Eagle extended immediate instruction - 6 bytes long
TR::InstOpCode::Mnemonic ei_immOp = TR::InstOpCode::BAD;
switch (memOp)
{
case TR::InstOpCode::A:
if (value == 0) return cursor;
if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
{
immOp = TR::InstOpCode::AHI;
}
else if (cg->canUseGoldenEagleImmediateInstruction(value))
{
// LL: If Golden Eagle - can use Add Immediate with max 32-bit value.
ei_immOp = TR::InstOpCode::AFI;
}
break;
case TR::InstOpCode::AG:
if (value == 0) return cursor;
if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
{
immOp = TR::InstOpCode::AGHI;
}
else if (cg->canUseGoldenEagleImmediateInstruction(value))
{
// LL: If Golden Eagle - can use Add Immediate with max 32-bit value.
ei_immOp = TR::InstOpCode::AGFI;
}
memOp = TR::InstOpCode::AGF;
break;
case TR::InstOpCode::CG:
if (value == 0)
{
if ((sourceRegister == targetRegister) && (cg->isActiveArithmeticCC(sourceRegister) || cg->isActiveLogicalCC(node, sourceRegister)))
{
return cursor;
}
else
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LTGR, node, sourceRegister, sourceRegister, preced);
return cursor;
}
}
if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
{
immOp = TR::InstOpCode::CGHI;
}
else if (cg->canUseGoldenEagleImmediateInstruction(value))
{
// LL: If Golden Eagle - can use Compare Immediate with max 32-bit value.
ei_immOp = TR::InstOpCode::CGFI;
}
memOp = TR::InstOpCode::CGF;
break;
case TR::InstOpCode::C:
if (value == 0)
{
if ((sourceRegister == targetRegister) && (cg->isActiveArithmeticCC(sourceRegister) || cg->isActiveLogicalCC(node, sourceRegister)))
{
return cursor;
}
else
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LTR, node, sourceRegister, sourceRegister, preced);
return cursor;
}
}
if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
{
immOp = TR::InstOpCode::CHI;
}
else if (cg->canUseGoldenEagleImmediateInstruction(value))
{
// LL: If Golden Eagle - can use Compare Immediate with max 32-bit value.
ei_immOp = TR::InstOpCode::CFI;
}
break;
case TR::InstOpCode::CL:
// Comparing to NULL, we can get away with LTR
if ((value == 0)&&(TR::ILOpCode::isEqualCmp(node->getOpCodeValue()) || TR::ILOpCode::isNotEqualCmp(node->getOpCodeValue())))
{
if (!targetRegister)
{
targetRegister = sourceRegister;
}
if (cg->isActiveArithmeticCC(sourceRegister) || cg->isActiveLogicalCC(node, sourceRegister))
{
return cursor;
}
else
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LTR, node, sourceRegister, sourceRegister, preced);
return cursor;
}
}
else
{
if (cg->canUseGoldenEagleImmediateInstruction(value))
{
// LL: If Golden Eagle - can use Compare Logical Immediate with max 32-bit value.
ei_immOp = TR::InstOpCode::CLFI;
targetRegister = sourceRegister;
}
// Number fits into LHI
else if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
{
TR::Register * constReg = NULL;
if (targetRegister != NULL && targetRegister != sourceRegister)
{
constReg = targetRegister;
}
else
{
// testing register pressure
if (!targetRegister)
targetRegister = sourceRegister;
break;
}
if (cond)
{
cond->addPostConditionIfNotAlreadyInserted(constReg, TR::RealRegister::AssignAny);
}
cursor = generateLoad32BitConstant(cg, node, value, constReg, true, preced, cond, NULL);
cursor = generateRRInstruction(cg, TR::InstOpCode::CLR, node, sourceRegister, constReg, cursor);
cg->stopUsingRegister(constReg);
return cursor;
}
// Big ugly number, go to lit pool
else
{
if (!targetRegister)
{
targetRegister = sourceRegister;
}
}
}
break;
case TR::InstOpCode::CLG:
case TR::InstOpCode::CLGF:
if ((value == 0)&&(TR::ILOpCode::isEqualCmp(node->getOpCodeValue()) || TR::ILOpCode::isNotEqualCmp(node->getOpCodeValue())))
{
if ((sourceRegister == targetRegister) && (cg->isActiveArithmeticCC(sourceRegister) || cg->isActiveLogicalCC(node, sourceRegister)))
{
return cursor;
}
else
{
cursor = generateRRInstruction(cg, TR::InstOpCode::LTGR, node, targetRegister, sourceRegister, preced);
return cursor;
}
}
if (cg->canUseGoldenEagleImmediateInstruction(value))
{
// LL: If Golden Eagle - can use Compare Logical Immediate with max 32-bit value.
ei_immOp = TR::InstOpCode::CLGFI;
break;
}
memOp = TR::InstOpCode::CLGF;
break;
case TR::InstOpCode::AL:
TR_ASSERT( sourceRegister != targetRegister, "generateS390ImmOp: AL requires two regs\n");
if (value == 0) return cursor;
if (cg->canUseGoldenEagleImmediateInstruction(value))
{
// LL: If Golden Eagle - can use Add Logical Immediate with max 32-bit value.
ei_immOp = TR::InstOpCode::ALFI;
}
else if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
{
cursor = generateRIInstruction(cg, TR::InstOpCode::LHI, node, sourceRegister, value, preced);
cursor = generateRRInstruction(cg, TR::InstOpCode::ALR, node, targetRegister, sourceRegister, cursor);
return cursor;
}
sourceRegister = targetRegister;
break;
case TR::InstOpCode::ALC:
TR_ASSERT( sourceRegister != targetRegister, "generateS390ImmOp: ALC requires two regs\n");
if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
{
cursor = generateRIInstruction(cg, TR::InstOpCode::LHI, node, sourceRegister, value, preced);
cursor = generateRRInstruction(cg, TR::InstOpCode::ALCR, node, targetRegister, sourceRegister, cursor);
return cursor;
}
else if (cg->canUseGoldenEagleImmediateInstruction(value))
{
cursor = generateRILInstruction(cg, TR::InstOpCode::IILF, node, sourceRegister, value, preced);
cursor = generateRRInstruction(cg, TR::InstOpCode::ALCR, node, targetRegister, sourceRegister, cursor);
return cursor;
}
else
{
sourceRegister = targetRegister;
}
break;
case TR::InstOpCode::SL:
if (value == 0) return cursor;
if (cg->canUseGoldenEagleImmediateInstruction(value))
{
// LL: If Golden Eagle - can use Add Logical Immediate with max 32-bit value.
ei_immOp=TR::InstOpCode::SLFI;
}
else if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
{
TR_ASSERT( sourceRegister != targetRegister, "generateS390ImmOp: SL requires two regs\n");
cursor = generateRIInstruction(cg, TR::InstOpCode::LHI, node, sourceRegister, value, preced);
cursor = generateRRInstruction(cg, TR::InstOpCode::SLR, node, targetRegister, sourceRegister, cursor);
return cursor;
}
sourceRegister = targetRegister;
break;
case TR::InstOpCode::SLB:
TR_ASSERT( sourceRegister != targetRegister, "generateS390ImmOp: SLB requires two regs\n");
if (value >= MIN_IMMEDIATE_VAL && value <= MAX_IMMEDIATE_VAL)
{
cursor = generateRIInstruction(cg, TR::InstOpCode::LHI, node, sourceRegister, value, preced);
cursor = generateRRInstruction(cg, TR::InstOpCode::SLBR, node, targetRegister, sourceRegister, cursor);
return cursor;
}
else if (cg->canUseGoldenEagleImmediateInstruction(value))
{
cursor = generateRILInstruction(cg, TR::InstOpCode::IILF, node, sourceRegister, value, preced);
cursor = generateRRInstruction(cg, TR::InstOpCode::SLBR, node, targetRegister, sourceRegister, cursor);
return cursor;
}
else
{
sourceRegister = targetRegister;
}
break;
case TR::InstOpCode::ALG:
if (value == 0) return cursor;
if (cg->canUseGoldenEagleImmediateInstruction(value))
{
// LL: If Golden Eagle - can use Add Logical Immediate with max 32-bit value.
ei_immOp = TR::InstOpCode::ALGFI;
break;
}
memOp=TR::InstOpCode::ALGF;
break;
case TR::InstOpCode::X:
{
if (value == 0)