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OMRTreeEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include <stdint.h>
#include <stdio.h>
#include <string.h>
#include "codegen/AheadOfTimeCompile.hpp"
#include "codegen/BackingStore.hpp"
#include "codegen/CodeGenerator.hpp"
#include "codegen/CodeGenerator_inlines.hpp"
#include "codegen/CodeGeneratorUtils.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/InstOpCode.hpp"
#include "codegen/Instruction.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LinkageConventionsEnum.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/RecognizedMethods.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterDependencyStruct.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/Relocation.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "codegen/PPCEvaluator.hpp"
#include "codegen/UnresolvedDataSnippet.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "compile/VirtualGuard.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CPU.hpp"
#include "env/CompilerEnv.hpp"
#include "env/ObjectModel.hpp"
#include "env/PersistentInfo.hpp"
#include "env/Processors.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/AutomaticSymbol.hpp"
#include "il/Block.hpp"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ParameterSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Annotations.hpp"
#include "infra/Assert.hpp"
#include "infra/Bit.hpp"
#include "infra/List.hpp"
#include "optimizer/Structure.hpp"
#include "p/codegen/OMRCodeGenerator.hpp"
#include "p/codegen/GenerateInstructions.hpp"
#include "p/codegen/LoadStoreHandler.hpp"
#include "p/codegen/PPCAOTRelocation.hpp"
#include "p/codegen/PPCHelperCallSnippet.hpp"
#include "p/codegen/PPCOpsDefines.hpp"
#include "p/codegen/PPCTableOfConstants.hpp"
#include "runtime/Runtime.hpp"
class TR_OpaqueClassBlock;
class TR_OpaqueMethodBlock;
#define MAX_PPC_ARRAYCOPY_INLINE 256
static inline bool alwaysInlineArrayCopy(TR::CodeGenerator *cg)
{
return false;
}
void loadFloatConstant(TR::CodeGenerator *cg, TR::InstOpCode::Mnemonic loadOp, TR::Node *node, TR::DataType type, void *value, TR::Register *trgReg)
{
int8_t length;
switch (type)
{
case TR::Float:
length = 4;
break;
case TR::Double:
length = 8;
break;
default:
TR_ASSERT_FATAL_WITH_NODE(node, false, "Cannot call loadFloatConstant with data type %s", TR::DataType::getName(type));
}
if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P10))
{
TR::Instruction *loadInstr;
TR::Register *tmpReg = NULL;
// Since we're using Trg1Imm instructions (to allow patching of the PC-relative offset), we
// have to use the prefixed form of the load without relying on MemoryReference expansion or
// the backend will reject the instruction as invalid.
switch (loadOp)
{
case TR::InstOpCode::lfs:
loadInstr = generateTrg1ImmInstruction(cg, TR::InstOpCode::plfs, node, trgReg, 0);
break;
case TR::InstOpCode::lfd:
loadInstr = generateTrg1ImmInstruction(cg, TR::InstOpCode::plfd, node, trgReg, 0);
break;
case TR::InstOpCode::lxvdsx:
tmpReg = cg->allocateRegister();
loadInstr = generateTrg1ImmInstruction(cg, TR::InstOpCode::paddi, node, tmpReg, 0);
generateTrg1MemInstruction(cg, loadOp, node, trgReg, TR::MemoryReference::createWithIndexReg(cg, NULL, tmpReg, length));
break;
default:
TR_ASSERT_FATAL_WITH_NODE(node, false, "Unhandled load instruction %s in loadFloatConstant", TR::InstOpCode(loadOp).getMnemonicName());
}
cg->findOrCreateFloatConstant(value, type, loadInstr, NULL, NULL, NULL);
if (tmpReg)
cg->stopUsingRegister(tmpReg);
return;
}
else if (cg->comp()->target().is64Bit())
{
int32_t tocOffset;
switch (type)
{
case TR::Float:
tocOffset = TR_PPCTableOfConstants::lookUp(*reinterpret_cast<float*>(value), cg);
break;
case TR::Double:
tocOffset = TR_PPCTableOfConstants::lookUp(*reinterpret_cast<double*>(value), cg);
break;
default:
TR_ASSERT_FATAL_WITH_NODE(node, false, "Invalid data type %s in loadFloatConstant", TR::DataType::getName(type));
}
if (tocOffset != PTOC_FULL_INDEX)
{
TR::Register *tmpReg = NULL;
TR::MemoryReference *memRef;
if (tocOffset < LOWER_IMMED || tocOffset > UPPER_IMMED)
{
tmpReg = cg->allocateRegister();
TR_ASSERT_FATAL_WITH_NODE(node, 0x00008000 != HI_VALUE(tocOffset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", tocOffset);
generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, tmpReg, cg->getTOCBaseRegister(), HI_VALUE(tocOffset));
memRef = TR::MemoryReference::createWithDisplacement(cg, tmpReg, LO_VALUE(tocOffset), length);
}
else
{
memRef = TR::MemoryReference::createWithDisplacement(cg, cg->getTOCBaseRegister(), tocOffset, length);
}
// TODO(#5383): We don't yet have a property flag to determine whether a load is
// indexed-form or not. For the time being, we only handle lxvdsx, as it's
// the only indexed-form load that can get here.
if (loadOp == TR::InstOpCode::lxvdsx)
memRef->forceIndexedForm(node, cg);
generateTrg1MemInstruction(cg, loadOp, node, trgReg, memRef);
if (tmpReg)
cg->stopUsingRegister(tmpReg);
return;
}
}
TR::Register *srcReg = cg->allocateRegister();
TR::Register *tmpReg = cg->comp()->target().is64Bit() ? cg->allocateRegister() : NULL;
TR::Instruction *q[4];
fixedSeqMemAccess(cg, node, 0, q, trgReg, srcReg, loadOp, length, NULL, tmpReg);
cg->findOrCreateFloatConstant(value, type, q[0], q[1], q[2], q[3]);
cg->stopUsingRegister(srcReg);
if (tmpReg)
cg->stopUsingRegister(tmpReg);
}
TR::Instruction *loadAddressConstantInSnippet(TR::CodeGenerator *cg, TR::Node * node, intptr_t address, TR::Register *trgReg, TR::Register *tempReg, TR::InstOpCode::Mnemonic opCode, bool isUnloadablePicSite, TR::Instruction *cursor)
{
if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P10))
{
cursor = generateTrg1ImmInstruction(cg, TR::InstOpCode::Op_pload, node, trgReg, 0, cursor);
cg->findOrCreateAddressConstant(&address, TR::Address, cursor, NULL, NULL, NULL, node, isUnloadablePicSite);
}
else
{
TR::Instruction *q[4];
bool isTmpRegLocal = false;
if (!tempReg && cg->comp()->target().is64Bit())
{
tempReg = cg->allocateRegister();
isTmpRegLocal = true;
}
cursor = fixedSeqMemAccess(cg, node, 0, q, trgReg, trgReg, opCode, sizeof(intptr_t), cursor, tempReg);
cg->findOrCreateAddressConstant(&address, TR::Address, q[0], q[1], q[2], q[3], node, isUnloadablePicSite);
if (isTmpRegLocal)
cg->stopUsingRegister(tempReg);
}
return cursor;
}
// loadAddressConstant could be merged with loadConstant 64-bit
TR::Instruction *
loadAddressConstant(
TR::CodeGenerator *cg,
bool isRelocatable,
TR::Node * node,
intptr_t value,
TR::Register *trgReg,
TR::Instruction *cursor,
bool isPicSite,
int16_t typeAddress)
{
if (isRelocatable)
return cg->loadAddressConstantFixed(node, value, trgReg, cursor, NULL, typeAddress);
return loadActualConstant(cg, node, value, trgReg, cursor, isPicSite);
}
// loadAddressConstant could be merged with loadConstant 64-bit
TR::Instruction *
loadAddressConstant(
TR::CodeGenerator *cg,
TR::Node * node,
intptr_t value,
TR::Register *trgReg,
TR::Instruction *cursor,
bool isPicSite,
int16_t typeAddress)
{
if (cg->comp()->compileRelocatableCode())
return cg->loadAddressConstantFixed(node, value, trgReg, cursor, NULL, typeAddress);
return loadActualConstant(cg, node, value, trgReg, cursor, isPicSite);
}
TR::Instruction *loadActualConstant(TR::CodeGenerator *cg, TR::Node * node, intptr_t value, TR::Register *trgReg, TR::Instruction *cursor, bool isPicSite)
{
if (cg->comp()->target().is32Bit())
return loadConstant(cg, node, (int32_t)value, trgReg, cursor, isPicSite);
return loadConstant(cg, node, (int64_t)value, trgReg, cursor, isPicSite);
}
TR::Instruction *loadConstant(TR::CodeGenerator *cg, TR::Node * node, int32_t value, TR::Register *trgReg, TR::Instruction *cursor, bool isPicSite)
{
TR::Compilation *comp = cg->comp();
intParts localVal(value);
int32_t ulit, llit;
TR::Instruction *temp = cursor;
if (cursor == NULL)
cursor = cg->getAppendInstruction();
if ((LOWER_IMMED <= localVal.getValue()) && (localVal.getValue() <= UPPER_IMMED))
{
cursor = generateTrg1ImmInstruction(cg, TR::InstOpCode::li, node, trgReg, localVal.getValue(), cursor);
}
else
{
ulit = localVal.getHighBitsSigned();
llit = localVal.getLowBits();
cursor = generateTrg1ImmInstruction(cg, TR::InstOpCode::lis, node, trgReg, ulit, cursor);
if (llit != 0 || isPicSite)
{
if (isPicSite)
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ori, node, trgReg, trgReg, value, cursor);
else
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ori, node, trgReg, trgReg, llit, cursor);
}
}
if (isPicSite)
{
// If the node is a call then value must be a class pointer (interpreter profiling devirtualization)
if (node->getOpCode().isCall() || node->isClassPointerConstant())
comp->getStaticPICSites()->push_front(cursor);
else if (node->isMethodPointerConstant())
comp->getStaticMethodPICSites()->push_front(cursor);
}
if (temp == NULL)
cg->setAppendInstruction(cursor);
return(cursor);
}
TR::Instruction *loadConstant(TR::CodeGenerator *cg, TR::Node * node, int64_t value, TR::Register *trgReg, TR::Instruction *cursor, bool isPicSite, bool useTOC)
{
// When loading 64-bit constants in 32-bit builds, we should not be using this function. This
// function assumes that 64-bit instructions are available and that intptr_t and int64_t are
// interchangeable.
TR_ASSERT_FATAL_WITH_NODE(node, cg->comp()->target().is64Bit(), "Should not use 64-bit loadConstant on 32-bit builds");
if ((TR::getMinSigned<TR::Int32>() <= value) && (value <= TR::getMaxSigned<TR::Int32>()))
{
return loadConstant(cg, node, (int32_t)value, trgReg, cursor, isPicSite);
}
if (cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P10))
return loadAddressConstantInSnippet(cg, node, value, trgReg, NULL, TR::InstOpCode::ld, isPicSite, cursor);
TR::Compilation *comp = cg->comp();
TR::Instruction *temp = cursor;
if (cursor == NULL)
cursor = cg->getAppendInstruction();
int32_t offset = PTOC_FULL_INDEX;
bool canUseTOC = (!TR::isJ9() || !isPicSite);
if (canUseTOC && useTOC)
offset = TR_PPCTableOfConstants::lookUp((int8_t *)&value, sizeof(int64_t), true, 0, cg);
if (offset != PTOC_FULL_INDEX)
{
offset *= TR::Compiler->om.sizeofReferenceAddress();
TR_PPCTableOfConstants::setTOCSlot(offset, value);
if (offset < LOWER_IMMED || offset > UPPER_IMMED)
{
TR_ASSERT_FATAL_WITH_NODE(node, 0x00008000 != cg->hiValue(offset), "TOC offset (0x%x) is unexpectedly high. Can not encode upper 16 bits into an addis instruction.", offset);
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addis, node, trgReg, cg->getTOCBaseRegister(), cg->hiValue(offset), cursor);
cursor = generateTrg1MemInstruction(cg,TR::InstOpCode::Op_load, node, trgReg, TR::MemoryReference::createWithDisplacement(cg, trgReg, LO_VALUE(offset), 8), cursor);
}
else
{
cursor = generateTrg1MemInstruction(cg,TR::InstOpCode::Op_load, node, trgReg, TR::MemoryReference::createWithDisplacement(cg, cg->getTOCBaseRegister(), offset, 8), cursor);
}
}
else
{
// Could not use TOC.
// Break up 64bit value into 4 16bit ones.
int32_t hhval, hlval, lhval, llval;
hhval = value >> 48;
hlval = (value>>32) & 0xffff;
lhval = (value>>16) & 0xffff;
llval = value & 0xffff;
// Load the upper 32 bits.
if ((hhval == -1 && (hlval & 0x8000) != 0) ||
(hhval == 0 && (hlval & 0x8000) == 0))
{
cursor = generateTrg1ImmInstruction(cg, TR::InstOpCode::li, node, trgReg, static_cast<int16_t>(hlval), cursor);
}
else
{
// lis trgReg, upper 16-bits
cursor = generateTrg1ImmInstruction(cg, TR::InstOpCode::lis, node, trgReg, static_cast<int16_t>(hhval) , cursor);
// ori trgReg, trgReg, next 16-bits
if (hlval != 0)
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ori, node, trgReg, trgReg, hlval, cursor);
}
// Shift upper 32 bits into place.
// shiftli trgReg, trgReg, 32
cursor = generateTrg1Src1Imm2Instruction(cg, TR::InstOpCode::rldicr, node, trgReg, trgReg, 32, CONSTANT64(0xFFFFFFFF00000000), cursor);
// oris trgReg, trgReg, next 16-bits
if (lhval != 0)
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::oris, node, trgReg, trgReg, lhval, cursor);
// ori trgReg, trgReg, last 16-bits
if (llval != 0 || isPicSite)
{
if (isPicSite)
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ori, node, trgReg, trgReg, value, cursor);
else
cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ori, node, trgReg, trgReg, llval, cursor);
}
if (isPicSite)
{
// If the node is a call then value must be a class pointer (interpreter profiling devirtualization)
if (node->getOpCode().isCall() || node->isClassPointerConstant())
comp->getStaticPICSites()->push_front(cursor);
else if (node->isMethodPointerConstant())
comp->getStaticMethodPICSites()->push_front(cursor);
}
}
if (temp == NULL)
cg->setAppendInstruction(cursor);
return cursor;
}
TR::Instruction *fixedSeqMemAccess(TR::CodeGenerator *cg, TR::Node *node, intptr_t addr, TR::Instruction **nibbles, TR::Register *srcOrTrg, TR::Register *baseReg, TR::InstOpCode::Mnemonic opCode, int32_t opSize, TR::Instruction *cursor, TR::Register *tempReg)
{
// Note: tempReg can be the same register as srcOrTrg. Caller needs to make sure it is right.
TR::Instruction *cursorCopy = cursor;
TR::InstOpCode op(opCode);
intptr_t hiAddr = cg->hiValue(addr);
intptr_t loAddr = LO_VALUE(addr);
int32_t idx;
TR::Compilation *comp = cg->comp();
nibbles[2] = nibbles[3] = NULL;
if (cursor == NULL)
cursor = cg->getAppendInstruction();
if (cg->comp()->target().is32Bit())
{
nibbles[0] = cursor = generateTrg1ImmInstruction(cg, TR::InstOpCode::lis, node, baseReg, (int16_t)hiAddr, cursor);
idx = 1;
}
else
{
if (tempReg == NULL)
{
nibbles[0] = cursor = generateTrg1ImmInstruction(cg, TR::InstOpCode::lis, node, baseReg, (int16_t)(hiAddr>>32), cursor);
nibbles[1] = cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ori, node, baseReg, baseReg, (hiAddr>>16)&0x0000FFFF, cursor);
cursor = generateTrg1Src1Imm2Instruction(cg, TR::InstOpCode::rldicr, node, baseReg, baseReg, 32, CONSTANT64(0xFFFFFFFF00000000), cursor);
nibbles[2] = cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::oris, node, baseReg, baseReg, hiAddr&0x0000FFFF, cursor);
}
else
{
nibbles[0] = cursor = generateTrg1ImmInstruction(cg, TR::InstOpCode::lis, node, tempReg, (int16_t)(hiAddr>>32), cursor);
nibbles[2] = cursor = generateTrg1ImmInstruction(cg, TR::InstOpCode::lis, node, baseReg, (int16_t)hiAddr, cursor);
nibbles[1] = cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::ori, node, tempReg, tempReg, (hiAddr>>16)&0x0000FFFF, cursor);
cursor = generateTrg1Src1Imm2Instruction(cg, TR::InstOpCode::rldimi, node, baseReg, tempReg, 32, CONSTANT64(0xFFFFFFFF00000000), cursor);
}
idx = 3;
}
// Can be used for any x-form instruction actually, not just lxvdsx
if (opCode == TR::InstOpCode::lxvdsx)
{
TR::MemoryReference *memRef;
if (cg->comp()->target().is64Bit() && tempReg)
{
nibbles[idx] = cursor = generateTrg1ImmInstruction(cg, TR::InstOpCode::li, node, tempReg, ((int32_t)loAddr)<<16>>16, cursor);
memRef = TR::MemoryReference::createWithIndexReg(cg, baseReg, tempReg, opSize);
}
else
{
nibbles[idx] = cursor = generateTrg1Src1ImmInstruction(cg, TR::InstOpCode::addi, node, baseReg, baseReg, ((int32_t)loAddr)<<16>>16, cursor);
memRef = TR::MemoryReference::createWithIndexReg(cg, NULL, baseReg, opSize);
}
cursor = generateTrg1MemInstruction(cg, opCode, node, srcOrTrg, memRef, cursor);
}
else
{
TR::MemoryReference *memRef = TR::MemoryReference::createWithDisplacement(cg, baseReg, ((int32_t)loAddr)<<16>>16, opSize);
if (!op.isStore())
nibbles[idx] = cursor = generateTrg1MemInstruction(cg, opCode, node, srcOrTrg, memRef, cursor);
else
nibbles[idx] = cursor = generateMemSrc1Instruction(cg, opCode, node, memRef, srcOrTrg, cursor);
}
// When using tempReg ensure no register spills occur in the middle of the fixed sequence
if (tempReg)
{
TR::RegisterDependencyConditions *dep = new (cg->trHeapMemory()) TR::RegisterDependencyConditions(0, 3, cg->trMemory());
if (srcOrTrg != tempReg && srcOrTrg != baseReg)
dep->addPostCondition(srcOrTrg, TR::RealRegister::NoReg);
dep->addPostCondition(tempReg, TR::RealRegister::NoReg);
dep->addPostCondition(baseReg, TR::RealRegister::NoReg, UsesDependentRegister | ExcludeGPR0InAssigner);
cursor = generateDepLabelInstruction(cg, TR::InstOpCode::label, node, TR::LabelSymbol::create(cg->trHeapMemory(),cg), dep);
}
if (cursorCopy == NULL)
cg->setAppendInstruction(cursor);
return cursor;
}
// Also handles iloadi
TR::Register *OMR::Power::TreeEvaluator::iloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *trgReg;
trgReg = cg->allocateRegister();
if (node->getSymbol()->isInternalPointer())
{
trgReg->setPinningArrayPointer(node->getSymbol()->castToInternalPointerAutoSymbol()->getPinningArrayPointer());
trgReg->setContainsInternalPointer();
}
TR::LoadStoreHandler::generateLoadNodeSequence(cg, trgReg, node, TR::InstOpCode::lwz, 4);
node->setRegister(trgReg);
return trgReg;
}
static bool nodeIsNeeded(TR::Node *checkNode, TR::Node *node)
{
bool result = (checkNode->getOpCode().isCall() ||
(checkNode != node && (checkNode->getOpCodeValue() == TR::aloadi || checkNode->getOpCodeValue() == TR::aload)));
TR::Node *child = NULL;
for (uint16_t i = 0; i < checkNode->getNumChildren() && !result; i++)
{
child = checkNode->getChild(i);
if (child->getOpCode().isCall())
result = true;
// If the class ptr load is feeding anything other than a nullchk it's probably needed
else if (child == node && !checkNode->getOpCode().isNullCheck())
result = true;
else if (child != node && (child->getOpCodeValue() == TR::aloadi || child->getOpCodeValue() == TR::aload))
result = true;
else
result = nodeIsNeeded(child, node);
if (result || child == node)
break;
}
return result;
}
// Also handles aloadi
TR::Register *OMR::Power::TreeEvaluator::aloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
// NEW to check for it feeding to a single vgdnop
static bool disableLoadForVGDNOP = (feGetEnv("TR_DisableLoadForVGDNOP") != NULL);
bool checkFeedingVGDNOP = !disableLoadForVGDNOP &&
node->getOpCodeValue() == TR::aloadi &&
node->getSymbolReference() &&
node->getReferenceCount() == 2 &&
!node->getSymbolReference()->isUnresolved() &&
node->getSymbolReference()->getSymbol()->getKind() == TR::Symbol::IsShadow;
if (OMR_UNLIKELY(checkFeedingVGDNOP))
{
TR::Node *topNode = cg->getCurrentEvaluationTreeTop()->getNode();
TR::SymbolReference *symRef = node->getSymbolReference();
int32_t index = symRef->getReferenceNumber();
int32_t numHelperSymbols = cg->symRefTab()->getNumHelperSymbols();
if (!nodeIsNeeded(topNode, node) &&
(comp->getSymRefTab()->isNonHelper(index, TR::SymbolReferenceTable::vftSymbol)) &&
topNode->getOpCodeValue() != TR::treetop && // side effects free
(!topNode->getOpCode().isNullCheck() || !topNode->getOpCode().isResolveCheck()))
{
// Search the current block for the feeding cmp to see
TR::TreeTop *tt = cg->getCurrentEvaluationTreeTop()->getNextTreeTop();
TR::Node *checkNode = NULL;
while (tt && (tt->getNode()->getOpCodeValue() != TR::BBEnd))
{
checkNode = tt->getNode();
if (cg->getSupportsVirtualGuardNOPing() &&
(checkNode->isNopableInlineGuard() || checkNode->isHCRGuard() || checkNode->isOSRGuard()) &&
(checkNode->getOpCodeValue() == TR::ificmpne || checkNode->getOpCodeValue() == TR::iflcmpne ||
checkNode->getOpCodeValue() == TR::ifacmpne) &&
checkNode->getFirstChild() == node)
{
// Try get the virtual guard
TR_VirtualGuard *virtualGuard = comp->findVirtualGuardInfo(checkNode);
if (!((comp->performVirtualGuardNOPing() || node->isHCRGuard() || node->isOSRGuard()) &&
comp->isVirtualGuardNOPingRequired(virtualGuard)) &&
virtualGuard->canBeRemoved())
{
break;
}
else
{
if (!topNode->getOpCode().isNullCheck() && !topNode->getOpCode().isResolveCheck())
node->decReferenceCount();
cg->recursivelyDecReferenceCount(node->getFirstChild());
TR::Register *tempReg = cg->allocateRegister(); // Empty register
node->setRegister(tempReg);
return tempReg;
}
}
tt = tt->getNextTreeTop();
}
}
}
TR::Register *trgReg;
if (!node->getSymbolReference()->getSymbol()->isInternalPointer())
{
if (node->getSymbolReference()->getSymbol()->isNotCollected())
trgReg = cg->allocateRegister();
else
trgReg = cg->allocateCollectedReferenceRegister();
}
else
{
trgReg = cg->allocateRegister();
trgReg->setPinningArrayPointer(node->getSymbolReference()->getSymbol()->castToInternalPointerAutoSymbol()->getPinningArrayPointer());
trgReg->setContainsInternalPointer();
}
// TODO Will this cause problems with evaluators that will inline aload and aloadi nodes?
#ifdef J9_PROJECT_SPECIFIC
bool isCompressedVft = TR::Compiler->om.generateCompressedObjectHeaders() && node->getSymbol()->isClassObject() && node->getSymbolReference() == comp->getSymRefTab()->findVftSymbolRef();
#else
bool isCompressedVft = false;
#endif
if (cg->comp()->target().is64Bit() && !isCompressedVft)
TR::LoadStoreHandler::generateLoadNodeSequence(cg, trgReg, node, TR::InstOpCode::ld, 8);
else
TR::LoadStoreHandler::generateLoadNodeSequence(cg, trgReg, node, TR::InstOpCode::lwz, 4);
#ifdef J9_PROJECT_SPECIFIC
if (node->getSymbolReference() == comp->getSymRefTab()->findVftSymbolRef())
TR::TreeEvaluator::generateVFTMaskInstruction(cg, node, trgReg);
#endif
node->setRegister(trgReg);
return trgReg;
}
// Also handles lloadi
TR::Register *OMR::Power::TreeEvaluator::lloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *trgReg;
if (cg->comp()->target().is64Bit())
{
trgReg = cg->allocateRegister();
TR::LoadStoreHandler::generateLoadNodeSequence(cg, trgReg, node, TR::InstOpCode::ld, 8);
}
else
{
trgReg = cg->allocateRegisterPair(cg->allocateRegister(), cg->allocateRegister());
TR::LoadStoreHandler::generatePairedLoadNodeSequence(cg, trgReg, node);
}
node->setRegister(trgReg);
return trgReg;
}
// Also handles bloadi
TR::Register *OMR::Power::TreeEvaluator::bloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *trgReg = cg->allocateRegister();
TR::LoadStoreHandler::generateLoadNodeSequence(cg, trgReg, node, TR::InstOpCode::lbz, 1);
node->setRegister(trgReg);
return trgReg;
}
// Also handles sloadi
TR::Register *OMR::Power::TreeEvaluator::sloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *trgReg = cg->allocateRegister();
TR::LoadStoreHandler::generateLoadNodeSequence(cg, trgReg, node, TR::InstOpCode::lha, 2);
node->setRegister(trgReg);
return trgReg;
}
// Also handles istorei
TR::Register *OMR::Power::TreeEvaluator::istoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR::Node *valueChild;
if (node->getOpCode().isIndirect())
{
valueChild = node->getSecondChild();
}
else
{
valueChild = node->getFirstChild();
}
bool reverseStore = false;
// TODO(#5684): Re-enable once issues with delayed indexed-form are corrected
static bool reverseStoreEnabled = feGetEnv("TR_EnableReverseLoadStore");
if (reverseStoreEnabled && valueChild->getOpCodeValue() == TR::ibyteswap &&
valueChild->getReferenceCount() == 1 &&
valueChild->getRegister() == NULL)
{
reverseStore = true;
cg->decReferenceCount(valueChild);
valueChild = valueChild->getFirstChild();
}
// Handle special cases
//
if (!reverseStore &&
valueChild->getRegister() == NULL &&
valueChild->getReferenceCount() == 1)
{
// Special case storing a float value into an int variable
//
if (valueChild->getOpCodeValue() == TR::fbits2i &&
!valueChild->normalizeNanValues())
{
TR::LoadStoreHandler::generateStoreNodeSequence(cg, cg->evaluate(valueChild->getFirstChild()), node, TR::InstOpCode::stfs, 4);
cg->decReferenceCount(valueChild->getFirstChild());
cg->decReferenceCount(valueChild);
return NULL;
}
}
TR::Register *valueReg = cg->evaluate(valueChild);
if (reverseStore)
TR::LoadStoreHandler::generateStoreNodeSequence(cg, valueReg, node, TR::InstOpCode::stwbrx, 4, true);
else
TR::LoadStoreHandler::generateStoreNodeSequence(cg, valueReg, node, TR::InstOpCode::stw, 4);
cg->decReferenceCount(valueChild);
if (comp->useCompressedPointers() && node->getOpCode().isIndirect())
node->setStoreAlreadyEvaluated(true);
return NULL;
}
// Also handles astorei
TR::Register *OMR::Power::TreeEvaluator::astoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR::Node *valueChild;
if (node->getOpCode().isIndirect())
valueChild = node->getSecondChild();
else
valueChild = node->getFirstChild();
TR::Register *valueReg = cg->evaluate(valueChild);
#ifdef J9_PROJECT_SPECIFIC
bool isCompressedVft = TR::Compiler->om.generateCompressedObjectHeaders() && (node->getSymbol()->isClassObject() || node->getSymbolReference() == comp->getSymRefTab()->findVftSymbolRef());
#else
bool isCompressedVft = false;
#endif
if (comp->target().is64Bit() && !isCompressedVft)
TR::LoadStoreHandler::generateStoreNodeSequence(cg, valueReg, node, TR::InstOpCode::std, 8);
else
TR::LoadStoreHandler::generateStoreNodeSequence(cg, valueReg, node, TR::InstOpCode::stw, 4);
cg->decReferenceCount(valueChild);
return NULL;
}
// Also handles lstorei
TR::Register *OMR::Power::TreeEvaluator::lstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR::Node *valueChild;
if (node->getOpCode().isIndirect())
{
valueChild = node->getSecondChild();
}
else
{
valueChild = node->getFirstChild();
}
bool reverseStore = false;
// TODO(#5684): Re-enable once issues with delayed indexed-form are corrected
static bool reverseStoreEnabled = feGetEnv("TR_EnableReverseLoadStore");
if (reverseStoreEnabled && valueChild->getOpCodeValue() == TR::lbyteswap &&
valueChild->getReferenceCount() == 1 &&
valueChild->getRegister() == NULL &&
cg->comp()->target().cpu.isAtLeast(OMR_PROCESSOR_PPC_P7))
{
reverseStore = true;
cg->decReferenceCount(valueChild);
valueChild = valueChild->getFirstChild();
}
// Handle special cases
//
if (!reverseStore &&
valueChild->getRegister() == NULL &&
valueChild->getReferenceCount() == 1)
{
// Special case storing a double value into a long variable
//
if (valueChild->getOpCodeValue() == TR::dbits2l &&
!valueChild->normalizeNanValues())
{
TR::LoadStoreHandler::generateStoreNodeSequence(cg, cg->evaluate(valueChild->getFirstChild()), node, TR::InstOpCode::stfd, 8);
cg->decReferenceCount(valueChild->getFirstChild());
cg->decReferenceCount(valueChild);
return NULL;
}
}
TR::Register *valueReg = cg->evaluate(valueChild);
if (comp->target().is64Bit())
{
if (reverseStore)
TR::LoadStoreHandler::generateStoreNodeSequence(cg, valueReg, node, TR::InstOpCode::stdbrx, 8, true);
else
TR::LoadStoreHandler::generateStoreNodeSequence(cg, valueReg, node, TR::InstOpCode::std, 8);
}
else
{
TR::LoadStoreHandler::generatePairedStoreNodeSequence(cg, valueReg, node);
}
cg->decReferenceCount(valueChild);
return NULL;
}
// Also handles bstorei
TR::Register *OMR::Power::TreeEvaluator::bstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *valueChild;
if (node->getOpCode().isIndirect())
{
valueChild = node->getSecondChild();
}
else
{
valueChild = node->getFirstChild();
}
if ((valueChild->getOpCodeValue()==TR::i2b ||
valueChild->getOpCodeValue()==TR::s2b) &&
valueChild->getReferenceCount()==1 && valueChild->getRegister()==NULL)
{
cg->decReferenceCount(valueChild);
valueChild = valueChild->getFirstChild();
}
TR::Register *valueReg = cg->evaluate(valueChild);
TR::LoadStoreHandler::generateStoreNodeSequence(cg, valueReg, node, TR::InstOpCode::stb, 1);
cg->decReferenceCount(valueChild);
return NULL;
}
// also handles isstore
TR::Register *OMR::Power::TreeEvaluator::sstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *valueChild;
if (node->getOpCode().isIndirect())
{
valueChild = node->getSecondChild();
}
else
{
valueChild = node->getFirstChild();
}
bool reverseStore = false;
// TODO(#5684): Re-enable once issues with delayed indexed-form are corrected
static bool reverseStoreEnabled = feGetEnv("TR_EnableReverseLoadStore");
if (reverseStoreEnabled && valueChild->getOpCodeValue() == TR::sbyteswap &&
valueChild->getReferenceCount() == 1 &&
valueChild->getRegister() == NULL)
{
reverseStore = true;
cg->decReferenceCount(valueChild);
valueChild = valueChild->getFirstChild();
}
if ((valueChild->getOpCodeValue()==TR::i2s) &&
valueChild->getReferenceCount()==1 && valueChild->getRegister()==NULL)
{
cg->decReferenceCount(valueChild);
valueChild = valueChild->getFirstChild();
}
TR::Register *valueReg = cg->evaluate(valueChild);
if (reverseStore)
TR::LoadStoreHandler::generateStoreNodeSequence(cg, valueReg, node, TR::InstOpCode::sthbrx, 2, true);
else
TR::LoadStoreHandler::generateStoreNodeSequence(cg, valueReg, node, TR::InstOpCode::sth, 2);
cg->decReferenceCount(valueChild);
return NULL;
}
TR::Register *OMR::Power::TreeEvaluator::vloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic opcode;
TR_RegisterKinds kind;
switch(node->getDataType())
{
case TR::VectorInt8:
case TR::VectorInt16:
case TR::VectorInt32:
case TR::VectorFloat:
opcode = TR::InstOpCode::lxvw4x;
kind = TR_VRF;
break;
case TR::VectorInt64:
opcode = TR::InstOpCode::lxvd2x;
kind = TR_VRF;
break;
case TR::VectorDouble:
opcode = TR::InstOpCode::lxvd2x;
kind = TR_VSX_VECTOR;
break;
default:
TR_ASSERT(false, "unknown vector load TRIL: unrecognized vector type %s\n", node->getDataType().toString()); return NULL;
}
TR::Register *dstReg = cg->allocateRegister(kind);
TR::LoadStoreHandler::generateLoadNodeSequence(cg, dstReg, node, opcode, 16, true);
node->setRegister(dstReg);
return dstReg;
}
TR::Register *OMR::Power::TreeEvaluator::vstoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::InstOpCode::Mnemonic opcode;
switch(node->getDataType())
{
case TR::VectorInt8:
case TR::VectorInt16:
case TR::VectorInt32:
case TR::VectorFloat:
opcode = TR::InstOpCode::stxvw4x; break;
case TR::VectorInt64:
case TR::VectorDouble:
opcode = TR::InstOpCode::stxvd2x; break;
default: TR_ASSERT(false, "unknown vector store TRIL: unrecognized vector type %s\n", node->getDataType().toString()); return NULL;
}
TR::Node *valueChild = node->getOpCode().isStoreDirect() ? node->getFirstChild() : node->getSecondChild();
TR::Register *valueReg = cg->evaluate(valueChild);
TR::LoadStoreHandler::generateStoreNodeSequence(cg, valueReg, node, opcode, 16, true);
cg->decReferenceCount(valueChild);
return NULL;
}
TR::Register *OMR::Power::TreeEvaluator::awrtbarEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
// The wrtbar IL op represents a store with side effects.
// Currently we don't use the side effect node. So just evaluate it and decrement the reference count.
TR::Node *sideEffectNode = node->getSecondChild();
cg->evaluate(sideEffectNode);
cg->decReferenceCount(sideEffectNode);
// Delegate the evaluation of the remaining children and the store operation to the storeEvaluator.
return TR::TreeEvaluator::astoreEvaluator(node, cg);
}
TR::Register *OMR::Power::TreeEvaluator::awrtbariEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
// The wrtbar IL op represents a store with side effects.
// Currently we don't use the side effect node. So just evaluate it and decrement the reference count.
TR::Node *sideEffectNode = node->getThirdChild();
cg->evaluate(sideEffectNode);
cg->decReferenceCount(sideEffectNode);
// Delegate the evaluation of the remaining children and the store operation to the storeEvaluator.
return TR::TreeEvaluator::astoreEvaluator(node, cg);
}
TR::Register *OMR::Power::TreeEvaluator::dwrtbarEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
// The wrtbar IL op represents a store with side effects.
// Currently we don't use the side effect node. So just evaluate it and decrement the reference count.
TR::Node *sideEffectNode = node->getSecondChild();
cg->evaluate(sideEffectNode);
cg->decReferenceCount(sideEffectNode);
// Delegate the evaluation of the remaining children and the store operation to the storeEvaluator.
return TR::TreeEvaluator::dstoreEvaluator(node, cg);
}