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FPTreeEvaluator.cpp
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/*******************************************************************************
* Copyright (c) 2000, 2021 IBM Corp. and others
*
* This program and the accompanying materials are made available under
* the terms of the Eclipse Public License 2.0 which accompanies this
* distribution and is available at http://eclipse.org/legal/epl-2.0
* or the Apache License, Version 2.0 which accompanies this distribution
* and is available at https://www.apache.org/licenses/LICENSE-2.0.
*
* This Source Code may also be made available under the following Secondary
* Licenses when the conditions for such availability set forth in the
* Eclipse Public License, v. 2.0 are satisfied: GNU General Public License,
* version 2 with the GNU Classpath Exception [1] and GNU General Public
* License, version 2 with the OpenJDK Assembly Exception [2].
*
* [1] https://www.gnu.org/software/classpath/license.html
* [2] http://openjdk.java.net/legal/assembly-exception.html
*
* SPDX-License-Identifier: EPL-2.0 OR Apache-2.0 OR GPL-2.0 WITH Classpath-exception-2.0 OR LicenseRef-GPL-2.0 WITH Assembly-exception
*******************************************************************************/
#include "x/codegen/FPTreeEvaluator.hpp"
#include <stdint.h>
#include <stdio.h>
#include "codegen/CodeGenerator.hpp"
#include "codegen/ConstantDataSnippet.hpp"
#include "env/FrontEnd.hpp"
#include "codegen/Linkage.hpp"
#include "codegen/Linkage_inlines.hpp"
#include "codegen/LinkageConventionsEnum.hpp"
#include "codegen/LiveRegister.hpp"
#include "codegen/Machine.hpp"
#include "codegen/MemoryReference.hpp"
#include "codegen/RealRegister.hpp"
#include "codegen/Register.hpp"
#include "codegen/RegisterConstants.hpp"
#include "codegen/RegisterDependency.hpp"
#include "codegen/RegisterPair.hpp"
#include "codegen/TreeEvaluator.hpp"
#include "compile/Compilation.hpp"
#include "compile/ResolvedMethod.hpp"
#include "compile/SymbolReferenceTable.hpp"
#include "control/Options.hpp"
#include "control/Options_inlines.hpp"
#include "env/CompilerEnv.hpp"
#include "env/TRMemory.hpp"
#include "env/jittypes.h"
#include "il/DataTypes.hpp"
#include "il/ILOpCodes.hpp"
#include "il/ILOps.hpp"
#include "il/LabelSymbol.hpp"
#include "il/MethodSymbol.hpp"
#include "il/Node.hpp"
#include "il/Node_inlines.hpp"
#include "il/ResolvedMethodSymbol.hpp"
#include "il/Symbol.hpp"
#include "il/SymbolReference.hpp"
#include "il/TreeTop.hpp"
#include "il/TreeTop_inlines.hpp"
#include "infra/Assert.hpp"
#include "infra/List.hpp"
#include "runtime/Runtime.hpp"
#include "x/codegen/FPBinaryArithmeticAnalyser.hpp"
#include "x/codegen/FPCompareAnalyser.hpp"
#include "x/codegen/OutlinedInstructions.hpp"
#include "x/codegen/RegisterRematerialization.hpp"
#include "x/codegen/X86FPConversionSnippet.hpp"
#include "x/codegen/X86Instruction.hpp"
#include "codegen/InstOpCode.hpp"
#include "x/codegen/X86Register.hpp"
namespace TR { class Instruction; }
// Only nodes that are referenced more than this number of times
// will be rematerializable.
//
#define REMATERIALIZATION_THRESHOLD 1
// Prototypes
TR::Register *OMR::X86::TreeEvaluator::coerceFPRToXMMR(TR::Node *node, TR::Register *fpRegister, TR::CodeGenerator *cg)
{
TR_ASSERT(fpRegister && fpRegister->getKind() == TR_X87, "incorrect register type for XMMR coercion\n");
TR::Register *xmmRegister = cg->allocateRegister(TR_FPR);
if (fpRegister->isSinglePrecision())
{
xmmRegister->setIsSinglePrecision();
TR::MemoryReference *tempMR = cg->machine()->getDummyLocalMR(TR::Float);
generateFPMemRegInstruction(TR::InstOpCode::FSTMemReg, node, tempMR, fpRegister, cg);
generateRegMemInstruction(TR::InstOpCode::MOVSSRegMem, node, xmmRegister, generateX86MemoryReference(*tempMR, 0, cg), cg);
}
else
{
TR::MemoryReference *tempMR = cg->machine()->getDummyLocalMR(TR::Double);
generateFPMemRegInstruction(TR::InstOpCode::DSTMemReg, node, tempMR, fpRegister, cg);
generateRegMemInstruction(cg->getXMMDoubleLoadOpCode(), node, xmmRegister, generateX86MemoryReference(*tempMR, 0, cg), cg);
}
cg->stopUsingRegister(fpRegister);
node->setRegister(xmmRegister);
return xmmRegister;
}
void OMR::X86::TreeEvaluator::coerceFPOperandsToXMMRs(TR::Node *node, TR::CodeGenerator *cg)
{
for (int i = 0; i < node->getNumChildren(); i++)
{
TR::Node *child = node->getChild(i);
TR::Register *reg = child->getRegister();
if (reg && reg->getKind() == TR_X87 /* && child->getReferenceCount() > 1 */)
{
TR::TreeEvaluator::coerceFPRToXMMR(child, reg, cg);
}
}
}
TR::Register *OMR::X86::TreeEvaluator::coerceXMMRToFPR(TR::Node *node, TR::Register *xmmRegister, TR::CodeGenerator *cg)
{
TR_ASSERT(xmmRegister && xmmRegister->getKind() == TR_FPR, "incorrect register type for FPR coercion\n");
TR::Register *fpRegister;
if (xmmRegister->isSinglePrecision())
{
fpRegister = cg->allocateSinglePrecisionRegister(TR_X87);
TR::MemoryReference *tempMR = cg->machine()->getDummyLocalMR(TR::Float);
generateMemRegInstruction(TR::InstOpCode::MOVSSMemReg, node, tempMR, xmmRegister, cg);
generateFPRegMemInstruction(TR::InstOpCode::FLDRegMem, node, fpRegister, generateX86MemoryReference(*tempMR, 0, cg), cg);
}
else
{
fpRegister = cg->allocateRegister(TR_X87);
TR::MemoryReference *tempMR = cg->machine()->getDummyLocalMR(TR::Double);
generateMemRegInstruction(TR::InstOpCode::MOVSDMemReg, node, tempMR, xmmRegister, cg);
generateFPRegMemInstruction(TR::InstOpCode::DLDRegMem, node, fpRegister, generateX86MemoryReference(*tempMR, 0, cg), cg);
}
return fpRegister;
}
void OMR::X86::TreeEvaluator::insertPrecisionAdjustment(TR::Register *reg,
TR::Node *root,
TR::CodeGenerator *cg)
{
TR::DataType dt;
TR::InstOpCode::Mnemonic opStore, opLoad;
TR::Node *node = root;
bool useFloatSet = true;
if (node->getOpCode().isBooleanCompare())
{
node = root->getFirstChild();
}
if ((node->getOpCode().isDouble() && (node->getOpCodeValue() != TR::f2d)) ||
(node->getOpCode().isBooleanCompare() && node->getFirstChild()->getDataType() != TR::Float) ||
node->getOpCodeValue() == TR::d2i ||
node->getOpCodeValue() == TR::d2l)
{
useFloatSet = false;
}
#ifdef DEBUG
else if (!(node->getOpCodeValue() == TR::f2d) &&
!(node->getOpCode().isFloat()) &&
!(node->getOpCodeValue() == TR::f2i) &&
!(node->getOpCodeValue() == TR::f2l))
{
diagnostic("insertPrecisionAdjustment() ==> invalid node type for precision adjustment!");
}
#endif
if (useFloatSet)
{
opStore = TR::InstOpCode::FSTPMemReg;
opLoad = TR::InstOpCode::FLDRegMem;
dt = TR::Float;
}
else
{
opStore = TR::InstOpCode::DSTPMemReg;
opLoad = TR::InstOpCode::DLDRegMem;
dt = TR::Double;
}
TR::MemoryReference *tempMR = (cg->machine())->getDummyLocalMR(dt);
generateFPMemRegInstruction(opStore, node, tempMR, reg, cg);
generateFPRegMemInstruction(opLoad, node, reg, tempMR, cg);
reg->resetNeedsPrecisionAdjustment();
reg->resetMayNeedPrecisionAdjustment();
}
TR::Register *OMR::X86::TreeEvaluator::fconstEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *targetRegister = cg->allocateSinglePrecisionRegister(TR_FPR);
if (node->getFloatBits() == 0)
{
generateRegRegInstruction(TR::InstOpCode::XORPSRegReg, node, targetRegister, targetRegister, cg);
}
else
{
TR::MemoryReference *tempMR = generateX86MemoryReference(cg->findOrCreate4ByteConstant(node, node->getFloatBits()), cg);
TR::Instruction *instr = generateRegMemInstruction(TR::InstOpCode::MOVSSRegMem, node, targetRegister, tempMR, cg);
setDiscardableIfPossible(TR_RematerializableFloat, targetRegister, node, instr, (intptr_t)node->getFloatBits(), cg);
}
node->setRegister(targetRegister);
return targetRegister;
}
TR::Register *OMR::X86::TreeEvaluator::dconstEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *targetRegister = cg->allocateRegister(TR_FPR);
if (node->getLongInt() == 0)
{
generateRegRegInstruction(TR::InstOpCode::XORPDRegReg, node, targetRegister, targetRegister, cg);
}
else
{
TR::MemoryReference *tempMR = generateX86MemoryReference(cg->findOrCreate8ByteConstant(node, node->getLongInt()), cg);
generateRegMemInstruction(cg->getXMMDoubleLoadOpCode(), node, targetRegister, tempMR, cg);
}
node->setRegister(targetRegister);
return targetRegister;
}
TR::Register *OMR::X86::TreeEvaluator::performFload(TR::Node *node, TR::MemoryReference *sourceMR, TR::CodeGenerator *cg)
{
TR::Register *targetRegister;
TR::Instruction *instr;
if (cg->comp()->target().is64Bit() &&
sourceMR->getSymbolReference().isUnresolved())
{
// The 64-bit mode XMM load instructions may be wider than 8-bytes (our patching
// window) but we won't know that for sure until after register assignment.
// Hence, the unresolved memory reference must be evaluated into a register
// first.
//
TR::Register *memReg = cg->allocateRegister(TR_GPR);
generateRegMemInstruction(TR::InstOpCode::LEA8RegMem, node, memReg, sourceMR, cg);
sourceMR = generateX86MemoryReference(memReg, 0, cg);
cg->stopUsingRegister(memReg);
targetRegister = cg->allocateSinglePrecisionRegister(TR_FPR);
instr = generateRegMemInstruction(TR::InstOpCode::MOVSSRegMem, node, targetRegister, sourceMR, cg);
}
else
{
targetRegister = cg->allocateSinglePrecisionRegister(TR_FPR);
instr = generateRegMemInstruction(TR::InstOpCode::MOVSSRegMem, node, targetRegister, sourceMR, cg);
setDiscardableIfPossible(TR_RematerializableFloat, targetRegister, node, instr, sourceMR, cg);
}
if (node->getOpCode().isIndirect())
cg->setImplicitExceptionPoint(instr);
node->setRegister(targetRegister);
return targetRegister;
}
// also handles TR::floadi
TR::Register *OMR::X86::TreeEvaluator::floadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::MemoryReference *tempMR = generateX86MemoryReference(node, cg);
TR::Register *targetRegister = TR::TreeEvaluator::performFload(node, tempMR, cg);
tempMR->decNodeReferenceCounts(cg);
return targetRegister;
}
TR::Register *OMR::X86::TreeEvaluator::performDload(TR::Node *node, TR::MemoryReference *sourceMR, TR::CodeGenerator *cg)
{
TR::Register *targetRegister;
TR::Instruction *instr;
if (cg->comp()->target().is64Bit() && sourceMR->getSymbolReference().isUnresolved())
{
// The 64-bit load instructions may be wider than 8-bytes (our patching
// window) but we won't know that for sure until after register assignment.
// Hence, the unresolved memory reference must be evaluated into a register
// first.
//
TR::Register *memReg = cg->allocateRegister(TR_GPR);
generateRegMemInstruction(TR::InstOpCode::LEA8RegMem, node, memReg, sourceMR, cg);
sourceMR = generateX86MemoryReference(memReg, 0, cg);
cg->stopUsingRegister(memReg);
}
targetRegister = cg->allocateRegister(TR_FPR);
instr = generateRegMemInstruction(cg->getXMMDoubleLoadOpCode(), node, targetRegister, sourceMR, cg);
if (node->getOpCode().isIndirect())
cg->setImplicitExceptionPoint(instr);
node->setRegister(targetRegister);
return targetRegister;
}
// also handles TR::dloadi
TR::Register *OMR::X86::TreeEvaluator::dloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::MemoryReference *tempMR = generateX86MemoryReference(node, cg);
TR::Register *targetRegister = TR::TreeEvaluator::performDload(node, tempMR, cg);
tempMR->decNodeReferenceCounts(cg);
return targetRegister;
}
TR::Register *OMR::X86::TreeEvaluator::floatingPointStoreEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
bool nodeIs64Bit = TR::TreeEvaluator::getNodeIs64Bit(node, cg);
bool nodeIsIndirect = node->getOpCode().isIndirect()? 1 : 0;
TR::Node *valueChild = node->getChild(nodeIsIndirect);
// Special case storing an int value into a float variable
//
if ((valueChild->getOpCodeValue() == TR::ibits2f || valueChild->getOpCodeValue() == TR::lbits2d) &&
!valueChild->getRegister())
{
// Turn the tree into the corresponding integer store
//
TR::Node *integerValueChild = valueChild->getFirstChild();
static TR::ILOpCodes integerOpCodes[2][2] = { {TR::istore, TR::lstore}, {TR::istorei, TR::lstorei} };
TR::Node::recreate(node, integerOpCodes[nodeIsIndirect][(valueChild->getOpCodeValue() == TR::ibits2f ? 0 : 1)]);
node->setChild(nodeIsIndirect, integerValueChild);
integerValueChild->incReferenceCount();
// valueChild is no longer used here
//
cg->recursivelyDecReferenceCount(valueChild);
// Generate an integer store
//
TR::TreeEvaluator::integerStoreEvaluator(node, cg);
return NULL;
}
TR::MemoryReference *tempMR = generateX86MemoryReference(node, cg);
TR::Instruction *exceptionPoint;
if (valueChild->getOpCode().isLoadConst())
{
if (nodeIs64Bit)
{
if (cg->comp()->target().is64Bit())
{
TR::Register *floatConstReg = cg->allocateRegister(TR_GPR);
if (valueChild->getLongInt() == 0)
{
generateRegRegInstruction(TR::InstOpCode::XOR8RegReg, node, floatConstReg, floatConstReg, cg);
}
else
{
generateRegImm64Instruction(TR::InstOpCode::MOV8RegImm64, node, floatConstReg, valueChild->getLongInt(), cg);
}
exceptionPoint = generateMemRegInstruction(TR::InstOpCode::S8MemReg, node, tempMR, floatConstReg, cg);
cg->stopUsingRegister(floatConstReg);
}
else
{
exceptionPoint = generateMemImmInstruction(TR::InstOpCode::S4MemImm4, node, tempMR, valueChild->getLongIntLow(), cg);
generateMemImmInstruction(TR::InstOpCode::S4MemImm4, node, generateX86MemoryReference(*tempMR, 4, cg), valueChild->getLongIntHigh(), cg);
}
}
else
{
exceptionPoint = generateMemImmInstruction(TR::InstOpCode::S4MemImm4, node, tempMR, valueChild->getFloatBits(), cg);
}
TR::Register *firstChildReg = valueChild->getRegister();
if (firstChildReg && firstChildReg->getKind() == TR_X87 && valueChild->getReferenceCount() == 1)
generateFPSTiST0RegRegInstruction(TR::InstOpCode::FSTRegReg, valueChild, firstChildReg, firstChildReg, cg);
}
else if (debug("useGPRsForFP") &&
(cg->getLiveRegisters(TR_GPR)->getNumberOfLiveRegisters() <
cg->getMaximumNumbersOfAssignableGPRs() - 1) &&
valueChild->getOpCode().isLoadVar() &&
valueChild->getRegister() == NULL &&
valueChild->getReferenceCount() == 1)
{
TR::Register *tempRegister = cg->allocateRegister(TR_GPR);
TR::MemoryReference *loadMR = generateX86MemoryReference(valueChild, cg);
generateRegMemInstruction(TR::InstOpCode::LRegMem(nodeIs64Bit), node, tempRegister, loadMR, cg);
exceptionPoint = generateMemRegInstruction(TR::InstOpCode::SMemReg(nodeIs64Bit), node, tempMR, tempRegister, cg);
cg->stopUsingRegister(tempRegister);
loadMR->decNodeReferenceCounts(cg);
}
else
{
TR::Register *sourceRegister = cg->evaluate(valueChild);
if (sourceRegister->getKind() == TR_FPR)
{
if (cg->comp()->target().is64Bit() &&
tempMR->getSymbolReference().isUnresolved())
{
if (!tempMR->getSymbolReference().getSymbol()->isShadow() && !tempMR->getSymbolReference().getSymbol()->isClassObject() && !tempMR->getSymbolReference().getSymbol()->isConstObjectRef())
{
// The 64-bit static case does not require the LEA instruction as we can resolve the address in the MOV reg, imm instruction preceeding the store.
//
exceptionPoint = generateMemRegInstruction(TR::InstOpCode::MOVSMemReg(nodeIs64Bit), node, tempMR, sourceRegister, cg);
}
else
{
// The 64-bit store instructions may be wider than 8-bytes (our patching
// window) but we won't know that for sure until after register assignment.
// Hence, the unresolved memory reference must be evaluated into a register
// first.
//
TR::Register *memReg = cg->allocateRegister(TR_GPR);
generateRegMemInstruction(TR::InstOpCode::LEA8RegMem, node, memReg, tempMR, cg);
TR::MemoryReference *mr = generateX86MemoryReference(memReg, 0, cg);
TR_ASSERT(nodeIs64Bit != sourceRegister->isSinglePrecision(), "Wrong operand type to floating point store\n");
exceptionPoint = generateMemRegInstruction(TR::InstOpCode::MOVSMemReg(nodeIs64Bit), node, mr, sourceRegister, cg);
tempMR->setProcessAsFPVolatile();
if (cg->comp()->getOption(TR_X86UseMFENCE))
insertUnresolvedReferenceInstructionMemoryBarrier(cg, TR::InstOpCode::MFENCE, exceptionPoint, tempMR, sourceRegister, tempMR);
else
insertUnresolvedReferenceInstructionMemoryBarrier(cg, LockOR, exceptionPoint, tempMR, sourceRegister, tempMR);
cg->stopUsingRegister(memReg);
}
}
else
{
TR_ASSERT(nodeIs64Bit != sourceRegister->isSinglePrecision(), "Wrong operand type to floating point store\n");
exceptionPoint = generateMemRegInstruction(TR::InstOpCode::MOVSMemReg(nodeIs64Bit), node, tempMR, sourceRegister, cg);
}
}
else
{
exceptionPoint = generateFPMemRegInstruction(TR::InstOpCode::FSTMemReg, node, tempMR, sourceRegister, cg);
}
}
cg->decReferenceCount(valueChild);
tempMR->decNodeReferenceCounts(cg);
if (nodeIsIndirect)
cg->setImplicitExceptionPoint(exceptionPoint);
return NULL;
}
TR::Register *OMR::X86::TreeEvaluator::fpReturnEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Register *returnRegister = cg->evaluate(node->getFirstChild());
TR_ASSERT(returnRegister, "Return node's child should evaluate to a register");
TR::Compilation *comp = cg->comp();
const TR::X86LinkageProperties &linkageProperties = cg->getProperties();
TR::RealRegister::RegNum machineReturnRegister =
(returnRegister->isSinglePrecision())? linkageProperties.getFloatReturnRegister() : linkageProperties.getDoubleReturnRegister();
/**
* On 32-bit targets, regardless of whether the target processor
* supports SSE or not, some linkages may still require a floating
* point value to be returned on the x87 stack (in ST0, for
* example). If so, the value in an XMM register needs to be
* coerced into the appropriate x87 register.
*/
if (cg->comp()->target().is32Bit() &&
(machineReturnRegister >= TR::RealRegister::FirstFPR && machineReturnRegister <= TR::RealRegister::LastFPR) &&
returnRegister->getKind() == TR_FPR)
{
// TODO: Modify linkage to allow the returned value to remain in an XMMR.
returnRegister = TR::TreeEvaluator::coerceXMMRToFPR(node->getFirstChild(), returnRegister, cg);
}
else if (returnRegister->mayNeedPrecisionAdjustment())
{
TR::TreeEvaluator::insertPrecisionAdjustment(returnRegister, node, cg);
}
// Restore the default FPCW if it has been forced to single precision mode.
//
if (comp->getJittedMethodSymbol()->usesSinglePrecisionMode() && !cg->useSSEForDoublePrecision())
{
generateMemInstruction(TR::InstOpCode::LDCWMem, node, generateX86MemoryReference(cg->findOrCreate2ByteConstant(node, DOUBLE_PRECISION_ROUND_TO_NEAREST), cg), cg);
}
TR::RegisterDependencyConditions *dependencies = NULL;
if (machineReturnRegister != TR::RealRegister::NoReg)
{
dependencies = generateRegisterDependencyConditions((uint8_t)1, 0, cg);
dependencies->addPreCondition(returnRegister, machineReturnRegister, cg);
dependencies->stopAddingConditions();
}
if (linkageProperties.getCallerCleanup())
{
generateFPReturnInstruction(TR::InstOpCode::RET, node, dependencies, cg);
}
else
{
generateFPReturnImmInstruction(TR::InstOpCode::RETImm2, node, 0, dependencies, cg);
}
if (comp->getJittedMethodSymbol()->getLinkageConvention() == TR_Private)
{
if (cg->useSSEForDoublePrecision())
comp->setReturnInfo((returnRegister->isSinglePrecision()) ? TR_FloatXMMReturn : TR_DoubleXMMReturn);
else
comp->setReturnInfo((returnRegister->isSinglePrecision()) ? TR_FloatReturn : TR_DoubleReturn);
}
cg->decReferenceCount(node->getFirstChild());
return NULL;
}
TR::Register *OMR::X86::TreeEvaluator::fpBinaryArithmeticEvaluator(TR::Node *node,
bool isFloat,
TR::CodeGenerator *cg)
{
if (cg->useSSEForSinglePrecision() && cg->useSSEForDoublePrecision())
{
return TR::TreeEvaluator::FloatingPointAndVectorBinaryArithmeticEvaluator(node, cg);
}
else
{
TR_X86FPBinaryArithmeticAnalyser temp(node, cg);
temp.genericFPAnalyser(node);
return node->getRegister();
}
}
TR::Register *OMR::X86::TreeEvaluator::fpUnaryMaskEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
static uint8_t MASK_FABS[] =
{
0xff, 0xff, 0xff, 0x7f,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
};
static uint8_t MASK_DABS[] =
{
0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, 0x7f,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
};
static uint8_t MASK_FNEG[] =
{
0x00, 0x00, 0x00, 0x80,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
};
static uint8_t MASK_DNEG[] =
{
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x80,
0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00,
};
uint8_t* mask;
TR::InstOpCode::Mnemonic opcode;
TR::InstOpCode::Mnemonic x87op;
switch (node->getOpCodeValue())
{
case TR::fabs:
mask = MASK_FABS;
opcode = TR::InstOpCode::PANDRegMem;
x87op = TR::InstOpCode::FABSReg;
break;
case TR::dabs:
mask = MASK_DABS;
opcode = TR::InstOpCode::PANDRegMem;
x87op = TR::InstOpCode::DABSReg;
break;
case TR::fneg:
mask = MASK_FNEG;
opcode = TR::InstOpCode::PXORRegMem;
x87op = TR::InstOpCode::FCHSReg;
break;
case TR::dneg:
mask = MASK_DNEG;
opcode = TR::InstOpCode::PXORRegMem;
x87op = TR::InstOpCode::DCHSReg;
break;
default:
TR_ASSERT(false, "Unsupported OpCode");
}
auto child = node->getFirstChild();
auto value = cg->evaluate(child);
auto result = child->getReferenceCount() == 1 ? value : cg->allocateRegister(value->getKind());
if (result != value && value->isSinglePrecision())
{
result->setIsSinglePrecision();
}
if (value->getKind() != TR_FPR) // Legacy supported for X87, to be deleted
{
if (value->needsPrecisionAdjustment())
TR::TreeEvaluator::insertPrecisionAdjustment(value, node, cg);
if (value->mayNeedPrecisionAdjustment())
result->setMayNeedPrecisionAdjustment();
if (result != value)
{
generateFPST0STiRegRegInstruction(value->isSinglePrecision() ? TR::InstOpCode::FLDRegReg : TR::InstOpCode::DLDRegReg, node, result, value, cg);
}
generateFPRegInstruction(x87op, node, result, cg);
}
else
{
// TODO 3-OP Optimization
if (result != value)
{
generateRegRegInstruction(TR::InstOpCode::MOVDQURegReg, node, result, value, cg);
}
generateRegMemInstruction(opcode, node, result, generateX86MemoryReference(cg->findOrCreate16ByteConstant(node, mask), cg), cg);
}
node->setRegister(result);
cg->decReferenceCount(child);
return result;
}
TR::Register *OMR::X86::TreeEvaluator::fpSqrtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
auto value = cg->evaluate(node->getFirstChild());
auto result = cg->allocateRegister(value->getKind());
if (value->isSinglePrecision())
{
result->setIsSinglePrecision();
}
generateRegRegInstruction(value->isSinglePrecision() ? TR::InstOpCode::SQRTSSRegReg : TR::InstOpCode::SQRTSDRegReg, node, result, value, cg);
node->setRegister(result);
cg->decReferenceCount(node->getFirstChild());
return result;
}
TR::Register *OMR::X86::TreeEvaluator::dsqrtEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *operand = node->getFirstChild();
TR::Register *opRegister = cg->evaluate(operand);
TR::Register *targetRegister = cg->allocateRegister(TR_FPR);
generateRegRegInstruction(TR::InstOpCode::SQRTSDRegReg, node, targetRegister, opRegister, cg);
node->setRegister(targetRegister);
cg->decReferenceCount(operand);
return targetRegister;
}
TR::Register *OMR::X86::TreeEvaluator::faddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return TR::TreeEvaluator::fpBinaryArithmeticEvaluator(node, true, cg);
}
TR::Register *OMR::X86::TreeEvaluator::daddEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return TR::TreeEvaluator::fpBinaryArithmeticEvaluator(node, false, cg);
}
TR::Register *OMR::X86::TreeEvaluator::fsubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return TR::TreeEvaluator::fpBinaryArithmeticEvaluator(node, true, cg);
}
TR::Register *OMR::X86::TreeEvaluator::dsubEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return TR::TreeEvaluator::fpBinaryArithmeticEvaluator(node, false, cg);
}
TR::Register *OMR::X86::TreeEvaluator::fmulEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return TR::TreeEvaluator::fpBinaryArithmeticEvaluator(node, true, cg);
}
TR::Register *OMR::X86::TreeEvaluator::dmulEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return TR::TreeEvaluator::fpBinaryArithmeticEvaluator(node, false, cg);
}
TR::Register *OMR::X86::TreeEvaluator::fdivEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return TR::TreeEvaluator::fpBinaryArithmeticEvaluator(node, true, cg);
}
TR::Register *OMR::X86::TreeEvaluator::ddivEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
return TR::TreeEvaluator::fpBinaryArithmeticEvaluator(node, false, cg);
}
TR::Register *OMR::X86::TreeEvaluator::fpRemEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
bool nodeIsDouble = node->getDataType() == TR::Double;
TR::Register *targetRegister;
TR::Compilation *comp = cg->comp();
const TR::X86LinkageProperties &linkageProperties = cg->getLinkage(comp->getJittedMethodSymbol()->getLinkageConvention())->getProperties();
TR::Node *divisor = node->getSecondChild();
TR::Node *dividend = node->getFirstChild();
if (cg->comp()->target().is64Bit())
{
// TODO: We should do this for IA32 eventually
TR::SymbolReference *helperSymRef = cg->symRefTab()->findOrCreateRuntimeHelper(nodeIsDouble ? TR_AMD64doubleRemainder : TR_AMD64floatRemainder);
targetRegister = TR::TreeEvaluator::performHelperCall(node, helperSymRef, nodeIsDouble ? TR::dcall : TR::fcall, false, cg);
}
else
{
TR::SymbolReference *helperSymRef = cg->symRefTab()->findOrCreateRuntimeHelper(nodeIsDouble ? TR_IA32doubleRemainderSSE : TR_IA32floatRemainderSSE);
targetRegister = TR::TreeEvaluator::performHelperCall(node, helperSymRef, nodeIsDouble ? TR::dcall : TR::fcall, false, cg);
}
if ((!nodeIsDouble && cg->useSSEForSinglePrecision()) ||
(nodeIsDouble && cg->useSSEForDoublePrecision()))
return targetRegister;
if (nodeIsDouble &&
(comp->getCurrentMethod()->isStrictFP() ||
comp->getOption(TR_StrictFP)))
{
// Strict double op.
//
targetRegister->setMayNeedPrecisionAdjustment();
targetRegister->setNeedsPrecisionAdjustment();
}
else if (!nodeIsDouble && !comp->getJittedMethodSymbol()->usesSinglePrecisionMode())
{
// Float op in a double-precision method.
//
targetRegister->setMayNeedPrecisionAdjustment();
targetRegister->setNeedsPrecisionAdjustment();
}
return targetRegister;
}
// also handles b2f, bu2f, s2f, su2f evaluators
TR::Register *OMR::X86::TreeEvaluator::i2fEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *target;
TR::MemoryReference *tempMR;
if (child->getRegister() == NULL &&
child->getReferenceCount() == 1 &&
child->getOpCode().isLoadVar())
{
tempMR = generateX86MemoryReference(child, cg);
target = cg->allocateSinglePrecisionRegister(TR_FPR);
generateRegMemInstruction(TR::InstOpCode::CVTSI2SSRegMem, node, target, tempMR, cg);
tempMR->decNodeReferenceCounts(cg);
}
else
{
TR::Register *intReg = cg->evaluate(child);
switch (node->getOpCodeValue())
{
case TR::b2f:
generateRegRegInstruction(TR::InstOpCode::MOVSXReg4Reg1, node, intReg, intReg, cg);
break;
case TR::bu2f:
generateRegRegInstruction(TR::InstOpCode::MOVZXReg4Reg1, node, intReg, intReg, cg);
break;
case TR::s2f:
generateRegRegInstruction(TR::InstOpCode::MOVSXReg4Reg2, node, intReg, intReg, cg);
break;
case TR::su2f:
generateRegRegInstruction(TR::InstOpCode::MOVZXReg4Reg2, node, intReg, intReg, cg);
break;
case TR::i2f:
break;
default:
TR_ASSERT(0, "INVALID OP CODE");
break;
}
target = cg->allocateSinglePrecisionRegister(TR_FPR);
generateRegRegInstruction(TR::InstOpCode::CVTSI2SSRegReg4, node, target, intReg, cg);
cg->decReferenceCount(child);
}
node->setRegister(target);
return target;
}
// also handles b2d, bu2d, s2d, su2d evaluators
TR::Register *OMR::X86::TreeEvaluator::i2dEvaluator(TR::Node *node, TR::CodeGenerator *cg)
{
TR::Node *child = node->getFirstChild();
TR::Register *target;
TR::MemoryReference *tempMR;
if (child->getRegister() == NULL && child->getReferenceCount() == 1 && child->getOpCode().isLoadVar())
{
tempMR = generateX86MemoryReference(child, cg);
target = cg->allocateRegister(TR_FPR);
generateRegMemInstruction(TR::InstOpCode::CVTSI2SDRegMem, node, target, tempMR, cg);
tempMR->decNodeReferenceCounts(cg);
}
else
{
TR::Register *intReg = cg->evaluate(child);
switch (node->getOpCodeValue())
{
case TR::b2d:
generateRegRegInstruction(TR::InstOpCode::MOVSXReg4Reg1, node, intReg, intReg, cg);
break;
case TR::bu2d:
generateRegRegInstruction(TR::InstOpCode::MOVZXReg4Reg1, node, intReg, intReg, cg);
break;
case TR::s2d:
generateRegRegInstruction(TR::InstOpCode::MOVSXReg4Reg2, node, intReg, intReg, cg);
break;
case TR::su2d:
generateRegRegInstruction(TR::InstOpCode::MOVZXReg4Reg2, node, intReg, intReg, cg);
break;
case TR::i2d:
break;
default:
TR_ASSERT(0, "INVALID OP CODE");
break;
}
target = cg->allocateRegister(TR_FPR);
generateRegRegInstruction(TR::InstOpCode::CVTSI2SDRegReg4, node, target, intReg, cg);
cg->decReferenceCount(child);
}
node->setRegister(target);
return target;
}
// General float/double convert to int
//
TR::Register *OMR::X86::TreeEvaluator::fpConvertToInt(TR::Node *node, TR::SymbolReference *helperSymRef, TR::CodeGenerator *cg)
{
TR::Compilation *comp = cg->comp();
TR_ASSERT(cg->comp()->target().is32Bit(), "AMD64 has enableSSE set, so it doesn't use this logic");
TR::Node *child = node->getFirstChild();
TR::Register *accReg = 0;
TR::Register *floatReg;
TR::Register *resultReg;
TR::MemoryReference *tempMR;
TR::X86RegMemInstruction *loadInstr;
TR::RegisterDependencyConditions *deps;
TR::LabelSymbol *startLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *reStartLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
TR::LabelSymbol *snippetLabel = TR::LabelSymbol::create(cg->trHeapMemory(),cg);
startLabel->setStartInternalControlFlow();
reStartLabel->setEndInternalControlFlow();
TR_ASSERT_FATAL(cg->comp()->compileRelocatableCode() || cg->comp()->isOutOfProcessCompilation() || cg->comp()->compilePortableCode() || cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE) == cg->getX86ProcessorInfo().supportsSSE(), "supportsSSE() failed\n");
TR_ASSERT_FATAL(cg->comp()->compileRelocatableCode() || cg->comp()->isOutOfProcessCompilation() || cg->comp()->compilePortableCode() || cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE2) == cg->getX86ProcessorInfo().supportsSSE2(), "supportsSSE2() failed\n");
bool optimizeF2IWithSSE = ( node->getOpCodeValue() == TR::f2i &&
cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE) );
bool optimizeD2IWithSSE2 = ( node->getOpCodeValue() == TR::d2i &&
cg->comp()->target().cpu.supportsFeature(OMR_FEATURE_X86_SSE2) );
if (!optimizeF2IWithSSE && !optimizeD2IWithSSE2)
{
floatReg = cg->evaluate(child);
if (floatReg && floatReg->needsPrecisionAdjustment())
{
TR::TreeEvaluator::insertPrecisionAdjustment(floatReg, node, cg);
}
}
generateLabelInstruction(TR::InstOpCode::label, node, startLabel, cg);
if (!optimizeF2IWithSSE && !optimizeD2IWithSSE2)
{
int16_t fpcw;
fpcw = comp->getJittedMethodSymbol()->usesSinglePrecisionMode() ?
SINGLE_PRECISION_ROUND_TO_ZERO : DOUBLE_PRECISION_ROUND_TO_ZERO;
fpcw = comp->getJittedMethodSymbol()->usesSinglePrecisionMode() ?
SINGLE_PRECISION_ROUND_TO_NEAREST : DOUBLE_PRECISION_ROUND_TO_NEAREST;
tempMR = (cg->machine())->getDummyLocalMR(TR::Int32);
generateMemInstruction(TR::InstOpCode::LDCWMem, node, generateX86MemoryReference(cg->findOrCreate2ByteConstant(node, fpcw), cg), cg);
generateFPMemRegInstruction(TR::InstOpCode::FISTMemReg, node, tempMR, floatReg, cg);
generateMemInstruction(TR::InstOpCode::LDCWMem, node, generateX86MemoryReference(cg->findOrCreate2ByteConstant(node, fpcw), cg), cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::L4RegMem, node, resultReg, generateX86MemoryReference(*tempMR, 0, cg), cg);
generateRegImmInstruction(TR::InstOpCode::CMP4RegImm4, node, resultReg, INT_MIN, cg);
generateLabelInstruction(TR::InstOpCode::JE4, node, snippetLabel, cg);
}
else
{
if (optimizeF2IWithSSE)
{
if (child->getReferenceCount() == 1 &&
child->getRegister() == 0 &&
child->getOpCode().isMemoryReference())
{
tempMR = generateX86MemoryReference(child, cg);
floatReg = cg->allocateRegister(TR_X87);
generateFPRegMemInstruction(TR::InstOpCode::FLDRegMem, node, floatReg, tempMR, cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::CVTTSS2SIReg4Mem, node, resultReg,
generateX86MemoryReference(*tempMR, 0, cg), cg);
tempMR->decNodeReferenceCounts(cg);
}
else
{
tempMR = (cg->machine())->getDummyLocalMR(TR::Float);
floatReg = cg->evaluate(child);
generateFPMemRegInstruction(TR::InstOpCode::FSTMemReg, node, tempMR, floatReg, cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::CVTTSS2SIReg4Mem, node, resultReg,
generateX86MemoryReference(*tempMR, 0, cg), cg);
}
}
else if (optimizeD2IWithSSE2)
{
if (child->getReferenceCount() == 1 &&
child->getRegister() == 0 &&
child->getOpCode().isMemoryReference())
{
tempMR = generateX86MemoryReference(child, cg);
floatReg = cg->allocateRegister(TR_X87);
generateFPRegMemInstruction(TR::InstOpCode::DLDRegMem, node, floatReg, tempMR, cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::CVTTSD2SIReg4Mem, node, resultReg,
generateX86MemoryReference(*tempMR, 0, cg), cg);
tempMR->decNodeReferenceCounts(cg);
}
else
{
tempMR = (cg->machine())->getDummyLocalMR(TR::Double);
floatReg = cg->evaluate(child);
generateFPMemRegInstruction(TR::InstOpCode::DSTMemReg, node, tempMR, floatReg, cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::CVTTSD2SIReg4Mem, node, resultReg,
generateX86MemoryReference(*tempMR, 0, cg), cg);
}
}
else
{
floatReg = cg->evaluate(child);
tempMR = (cg->machine())->getDummyLocalMR(TR::Int32);
generateFPMemRegInstruction(TR::InstOpCode::FISTMemReg, node, tempMR, floatReg, cg);
resultReg = cg->allocateRegister();
loadInstr = generateRegMemInstruction(TR::InstOpCode::L4RegMem, node, resultReg,
generateX86MemoryReference(*tempMR, 0, cg), cg);
}
generateRegImmInstruction(TR::InstOpCode::CMP4RegImm4, node, resultReg, INT_MIN, cg);
generateLabelInstruction(TR::InstOpCode::JE4, node, snippetLabel, cg);
}
// Create the conversion snippet.
//
cg->addSnippet( new (cg->trHeapMemory()) TR::X86FPConvertToIntSnippet(reStartLabel,
snippetLabel,
helperSymRef,
loadInstr,
cg) );
// Make sure the int register(s) is/are assigned to something.
//
if (accReg)
{
deps = generateRegisterDependencyConditions((uint8_t) 0, 2, cg);
deps->addPostCondition(accReg, TR::RealRegister::eax, cg);
deps->addPostCondition(resultReg, TR::RealRegister::NoReg, cg);
}
else
{
deps = generateRegisterDependencyConditions((uint8_t) 0, 1, cg);
deps->addPostCondition(resultReg, TR::RealRegister::NoReg, cg);
}