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Develop -> Master #53
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pads being used as placeholders for the analog I/O with the new sky130_ef_io__analog_pad. The remaining 3 pads continue to use sky130_fd_io__top_power_hvc_wpadv2, providing a few clamp circuits that users can connect to additional analog power supplies if they need them.
allow the SoC to respond to triggered events from the user project instead of having to poll for them.
signals. Otherwise, per the existing MPW-one caravel chip, the top-level routing is not generating a clock tree and so creates a long and highly resistive network for clock and reset that will probably cause the clock rate to have to be significantly reduced for the serial load to work. The modification means that the management SoC only drives clock and reset on the first control block on each side. The signal transfer then ripples from the front to the end of each serial chain, mitigating timing issues.
…velop Pulling manifest update
each logic analyzer input from the user project to the management SoC. This allows the user to ignore any bits not being used, and they do not need to be wired out from the user project. (2) Made a simple change to the way the logic analyzer reads inputs, which decouples inputs and outputs. This doubles the number of available logic analyzer bits by allowing simultaneous use of 128 inputs and 128 outputs. (3) Added logic to the management protect block so that the output enable signals work as advertised and put the output into a high-impedence state. Previously it could be used by the user project to selectively multiplex the output, but did not prevent the output from being driven.
the entire set of 128 bits, with a simultaneous data capture.
…velop Missed pulling the manifest update.
by Manar Abdelatty, where the references were to sky130_fd_io__analog_pad, which was done before I decided to make the name sky130_ef_io__analog_pad.
- fixed placement of io_in_3v3 pins - dropped power straps
- add target for running xor against analog wrapper - change open_pdks url to github for now till opencircuit design is stable
- dropeed chip_io from CI, needs to be rebuilt with latest pdk - currently fails due to name changes from ef_io -> fd_io
user analog project wrapper to maximize area and to bring the power supplies directly into the user core as stub connections. Redrew the analog connections larger to match the pads, and added the clamp connections on the three remaining power pads in the middle.
…velop Merging updates that happened since I started working on the layout.
reflect what I need all of them to look like.
IRQ support for user_project_wrapper, make pdk change from master -> main, documentation, analog support |
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