GitHub - einstein07/Vivado-IP-and-Resource-Usage: Creates a simple major arpeggiator using a Vivado IP core on a Nexys A7 FPGA board.

einstein07 / Vivado-IP-and-Resource-Usage Public

Creates a simple major arpeggiator using a Vivado IP core on a Nexys A7 FPGA board.

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Name		Name	Last commit message	Last commit date
Latest commit History 7 Commits
FullSine		FullSine
Prac sources		Prac sources
Vivado IP and Resource Usage.cache/wt		Vivado IP and Resource Usage.cache/wt
Vivado IP and Resource Usage.hw		Vivado IP and Resource Usage.hw
quartsine		quartsine
Vivado IP and Resource Usage.xpr		Vivado IP and Resource Usage.xpr