Test PCB for CARAVEL ASIC manufactured by efables.com in Open Source Shuttles to check HyperRAM memory controller IP connected to RISC-V through Wishbone bus.
HyperRAM controller was submitted in MPW-2 as part of multi project: https://platform.efabless.com/projects/66 and in MPW-3 on its own (with additional 1kB of OpenRAM): https://platform.efabless.com/projects/501
HyperRAM controller IP was created to work with Cypress S27KL0641: https://github.com/embelon/wb_hyperram