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This repository was archived by the owner on Aug 30, 2021. It is now read-only.
VSU: Describe various clock periods in terms of sample clock period
When calculating these numbers, I took the frequencies listed in the hw docs and calculated their periods in cycles, rounded to whole numbers. When looking at this again, it's clear that all of them work out to be simple multiples of the sample clock period, which is highly likely, assuming there's a single clock divider for all of these circuits, followed by even simpler/smaller counters.
This patch only changes how these constants are calculated; a more accurate/faithful implementation would update these counters only when the sample clock period occurs. I may implement this in a later patch.
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