Add hooks and features for 10/25G implementation

[jersey99]

Liteeth is very feature rich. However, lacking >1G functionality. Following modifications have made a simple working 10G liteth core that can be tested on hardware.

For motivation

Liteeth lacked a MAC implementation of datawidth > 8bits. So, in order to facilitate wider lanes for XGMII, extended the datawidths of all the modules (PHY, MAC, ARP, IP, and all their supporting modules etc have been modified.

1. The XGMII BASE-R chapter 46 phy implementing the incomplete XGMII standard is in liteeth/phy/xgmii.py
2. Liteth written in Migen, can be converted to Verilog which is simulated using Verilator. The Linux TUN/TAP user space interface mixed with Verilator simulation written in C/C++ takes a stream of data from LiteEthMAC/PHY, and is sent to the Linux Kernel's virtual networking interface (and vice versa). Since the Linux Kernel's TAP interface only provides MAC and higher layers, the PHY interface can actually be tested in the C/C++ layer by decoing PHY signals into data words before passing it into the TAP interface. This is tested in simulation over verilator and tapcfg at litex/build/sim/core/modules/xgmii_ethernet/xgmii_ethernet.c This is an extension of the existing ethernet.c test. The xgmii_ethernet.c can perhaps be extended to all widths and controls for MII/GMII/RGMII and perhaps even the PCS/PMA.
3. Liteeth uses streaming interface as interconnect between modules. When modules have byte wide boundaries and the datawidth remains 1byte, the interconnect is arguably “simpler”. When the datawidth is higher, the header-payload boundaries don't align with datawidth boundaries, which requires modifications to the packetizers and streams. Now implemented at XGMII branch on litex and liteeth
   Both 1G and 10G use the same codepath.
4. After these modifications, the Xilinx 10G/25G "free" but proprietary PCS/PMA IP core to test it on hardware. With this I have managed to get the Tx side sending packets to a PC over a 10G ethernet but not the Rx side successfully receiving yet. Hardware used HTG-940 with a XCVU190 (the ultrascale version). Can also be tested on a board with a Kintex-7 with an SFP connector connected to a > 10Gbps transceiver.

IP Fragmentation:

Typical ethernet MTU is 1530 bytes, from the motivation section above, one can imagine bumping up the MTU to 9000 on more controlled networks running scientific experiments.
IP Fragmentation is also a useful feature when it comes to pushing the maximum packet size to the fully available 65536 (IP maximum packet size). This is now implemented inside ip.py

TODO

• 1. Synthesize the design for a 25G speed to see the limitations
• 2. VLAN tagging to help route high bandwidth data.
• 3. Remove the dependence on PCS/PMA implementation to avoid yet another Xilinx core. Note that Alex Forencich's design mentioned above implements the PCS layer. As this really removes the dependency on the Xilinx core and can even perhaps speed up synthesis time. The standard is Chapter 49 PCS/PMA
• 4. 64bit dw CRC checker needs to be fully tested.
• 5. Rx side out of the core seems to be partially broken in hardware.
• 6. Hardwired ARP table: I have no choice but to use this as the Rx side of the XGMII doesn't work yet on hardware
• 7. Pass in the ARP table at core instantiation time.
• 8. Override eth_mtu setting option into the core, at instantiaion time.

[rowanG077]

What's the status of this? I really would like to use the ColorLight 5A-7B ethernet.

[enjoy-digital]

There are some work planned in the next months on this, if you want to use Ethernet with the ColorLight, it should already be possible with the MAC + CPU using: --with-ethernet (that's the hardware stack that is currently causing the timing issues).

[jersey99]

@enjoy-digital @rowanG077 FyI, I have seen some timing errors while synthesizing for the 25G core. However none for the 10G core at standard 156.25MHz. I'm curious to know more about the usage with the ColorLight boaRd though!

[enjoy-digital]

@jersey99: thanks for the infos, the Colorlight is an in-expensive ECP5 board (15$: https://www.google.com/search?q=colorlight+7a+75b) that is supported by LiteX: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/colorlight_5a_75x.py, the timings are currently not met with the 1Gbps/8-bit/UDP-IP stack and i was thinking 32-bit data-width to lower the clock freq.

[jersey99]

@enjoy-digital Thanks for the clarification, makes sense. That board is pretty sweet!

[enjoy-digital]

10Gbps Ethernet has been tested successfully in both TX/RX on a KC705/SFP with 32-bit and 64-bit data-path. This PR has been used as an initial step and various changes have been done to fix issue and improve timings. This will be integrated in LiteEth in the next weeks.

[david-sawatzke]

For everyone interested in this: An initial 64/32 bit MAC as well as a XGMII PHY implementation have been added to liteeth. The surrounding code and the UDP/IP stack hast't changed yet to take advantage of this.

This means a gigabit connection with a wider MAC or a XGMII PHY can currently only work with the softcore, which limits bandwith severely.

[enjoy-digital]

We can probably close this thanks to @lschuermann and @david-sawatzke who finished the 10Gbps support last year.