Trying to interact with UART via Rust binary (stuck at liftoff) #1935

roby2014 · 2024-04-20T21:45:47Z

Hello. Not sure if the right place to ask, but here I go:

been trying to flash a rust program to my ecp5 fpga (colorlight 5a-75e). however when booting, im not getting the expected output.

#![no_std]
#![no_main]

extern crate panic_halt;

use riscv_rt::entry;
use litex_pac as pac;

fn uart_write(uart: &pac::Uart, value: u8) {
    while uart_txfull_read(uart) != 0 {}
    uart.rxtx().write(|w| unsafe { w.bits(value.into()) });
    uart.ev_pending().write(|w| unsafe { w.bits(0x1) });
}

fn uart_txfull_read(uart: &pac::Uart) -> u8 {
    return uart.txfull().read().bits() as u8;
}

fn hprint(uart: &pac::Uart, s: &str) {
    for c in s.bytes() {
        uart_write(uart, c);
    }
}

#[entry]
fn main() -> ! {
    let peripherals = unsafe { pac::Peripherals::steal() };
    let uart = peripherals.uart;

    loop {
        hprint(&uart, "a");
    }
}

however, it gets stuck at liftoff:

litex> reboot

        __   _ __      _  __
       / /  (_) /____ | |/_/
      / /__/ / __/ -_)>  <
     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2024 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Apr 20 2024 19:46:07
 BIOS CRC passed (8472a90b)

 LiteX git sha1: c2fd1e9a

--=============== SoC ==================--
CPU:            VexRiscv @ 25MHz
BUS:            wishbone 32-bit @ 4GiB
CSR:            32-bit data
ROM:            32.0KiB
SRAM:           8.0KiB
MAIN-RAM:       16.0KiB

--========== Initialization ============--
Memtest at 0x40000000 (16.0KiB)...
  Write: 0x40000000-0x40004000 16.0KiB   
   Read: 0x40000000-0x40004000 16.0KiB   
Memtest OK
Memspeed at 0x40000000 (Sequential, 16.0KiB)...
  Write speed: 37.7MiB/s
   Read speed: 19.0MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[LITEX-TERM] Received firmware download request from the device.
[LITEX-TERM] Uploading target/riscv32i-unknown-none-elf/debug/app.bin to 0x40000000 (7876 bytes)...
[LITEX-TERM] Upload calibration... (inter-frame: 10.00us, length: 64)
[LITEX-TERM] Upload complete (10.0KB/s).
[LITEX-TERM] Booting the device.
[LITEX-TERM] Done.
Executing booted program at 0x40000000

--============= Liftoff! ===============--

any idea how I can debug this? ive tried uploading a c binary (this one and works fine.

this is how im building my soc:

class BaseSoC(SoCCore):
    def __init__(self, version, revision):
        # 25 MHz
        sys_clk_freq = int(25e6)

        # SoC with CPU
        platform = colorlight_5a_75e.Platform(revision)
        SoCCore.__init__(self, platform,
            cpu_type                 = "vexriscv",
            clk_freq                 = sys_clk_freq,
            ident                    = f"LiteX RISC-V CPU Test SoC {version}", ident_version=True,
            integrated_rom_size      = 0x8000,
            integrated_main_ram_size = 0x4000)

        # Clock Reset Generation
        self.submodules.crg = CRG(platform.request("clk25"))


# Build --------------------------------------------------------------------------------------------

def main():
    parser = argparse.ArgumentParser(description="LiteX RISC-V SoC on Colorlight 5A-75E")
    builder_args(parser)
    soc_core_args(parser)
    trellis_args(parser)
    parser.add_argument("--build", action="store_true", help="Build bitstream")
    parser.add_argument("--load",  action="store_true", help="Load bitstream")
    parser.add_argument("--cable", default="ft232",    help="openFPGALoader JTAG probe model")
    parser.add_argument("--revision", default="6.0",  help="Colorlight 5A-75E model revision")
    args = parser.parse_args()

    soc = BaseSoC("5A-75E", revision=args.revision)

    builder = Builder(soc, **builder_argdict(args))
    builder.build(**trellis_argdict(args), run=args.build)

    if args.load:
        extra_args = ""
        if args.cable == "ft232RL":
            extra_args = "--pins=RXD:RTS:TXD:CTS"
        elif args.cable == "usb-blaster":
            extra_args = f"--probe-firmware {os.environ['QUARTUSPATH']}"
            
        bitstream_file = os.path.join(builder.gateware_dir, f'{soc.build_name}.bit')
        cmd = f"openFPGALoader --cable {args.cable} {extra_args} {bitstream_file}"
        print(f"Uploading bitstream file: {bitstream_file}")
        print(f"JTAG cable: {args.cable}")
        print(f"Running command: {cmd}")
        os.system(cmd)

if __name__ == "__main__":
    main()

The text was updated successfully, but these errors were encountered:

AndrewD · 2024-04-20T21:54:08Z

You could use litescope to capture the soc bus address to see where your code is going. But if you use the sim as per your other issue you are probably already getting a vcd file that shows the full internal state of the design.

roby2014 · 2024-04-21T00:00:23Z

Program works in simulation with

litex_sim --output-dir=target/litex_sim --cpu-type=vexriscv --rom-init=$1.bin --no-compile-software --csr-csv "csr.csv"

Hmm...

#--------------------------------------------------------------------------------
# Auto-generated by LiteX (c2fd1e9a) on 2024-04-21 00:56:11
#--------------------------------------------------------------------------------
csr_base,ctrl,0xf0000000,,
csr_base,identifier_mem,0xf0000800,,
csr_base,timer0,0xf0001000,,
csr_base,uart,0xf0001800,,
csr_register,ctrl_reset,0xf0000000,1,rw
csr_register,ctrl_scratch,0xf0000004,1,rw
csr_register,ctrl_bus_errors,0xf0000008,1,ro
csr_register,timer0_load,0xf0001000,1,rw
csr_register,timer0_reload,0xf0001004,1,rw
csr_register,timer0_en,0xf0001008,1,rw
csr_register,timer0_update_value,0xf000100c,1,rw
csr_register,timer0_value,0xf0001010,1,ro
csr_register,timer0_ev_status,0xf0001014,1,ro
csr_register,timer0_ev_pending,0xf0001018,1,rw
csr_register,timer0_ev_enable,0xf000101c,1,rw
csr_register,uart_rxtx,0xf0001800,1,rw
csr_register,uart_txfull,0xf0001804,1,ro
csr_register,uart_rxempty,0xf0001808,1,ro
csr_register,uart_ev_status,0xf000180c,1,ro
csr_register,uart_ev_pending,0xf0001810,1,rw
csr_register,uart_ev_enable,0xf0001814,1,rw
csr_register,uart_txempty,0xf0001818,1,ro
csr_register,uart_rxfull,0xf000181c,1,ro
constant,config_clock_frequency,1000000,,
constant,config_cpu_has_interrupt,None,,
constant,config_cpu_reset_addr,0,,
constant,config_cpu_has_dcache,None,,
constant,config_cpu_has_icache,None,,
constant,config_cpu_type_vexriscv,None,,
constant,config_cpu_variant_standard,None,,
constant,config_cpu_name,vexriscv,,
constant,config_cpu_human_name,vexriscv,,
constant,config_cpu_nop,nop,,
constant,config_rom_init,1,,
constant,config_csr_data_width,32,,
constant,config_csr_alignment,32,,
constant,config_bus_standard,wishbone,,
constant,config_bus_data_width,32,,
constant,config_bus_address_width,32,,
constant,config_bus_bursting,0,,
constant,config_cpu_interrupts,2,,
constant,timer0_interrupt,1,,
constant,uart_interrupt,0,,
memory_region,rom,0x00000000,131072,cached
memory_region,sram,0x10000000,8192,cached
memory_region,csr,0xf0000000,65536,io

enjoy-digital · 2024-06-13T10:24:20Z

Hi @roby2014,

do you still have the issue? If working in simulation from ROM, you could also try to run it from MAIN_RAM (--ram-init) in simulation, this way you'll be in condition very similar to your hardware test). I don't have that much experience with Rust, but is your program configured to run from MAIN_RAM (0x4000_0000). If working in simulation in these condition, I expect it to also work on hardware. If not working, you'll have the full visibility on the SoC signals with --trace

roby2014 · 2024-06-13T22:31:09Z

hi @enjoy-digital . I've not looked at this since I created this issue.

so, running the above program in simulation work with rom init, but does not with ram, so im supposing the hardware issue is the same as the simulation + ram.

Please see the following logs if they help:

--rom-init

set -e
riscv64-elf-objcopy $1 -O binary $1.bin
litex_sim --output-dir=target/litex_sim --cpu-type=vexriscv --rom-init=$1.bin --no-compile-software --csr-csv "csr.csv"

output:

(.venv) [roby@thonkpad firmware]$ cargo run
   Compiling litex-pac v0.1.0 (/home/roby/repos/colorlight-litex-rs/litex-pac)
   Compiling firmware v0.1.0 (/home/roby/repos/colorlight-litex-rs/firmware)
    Finished dev [unoptimized + debuginfo] target(s) in 0.52s
     Running `/home/roby/repos/colorlight-litex-rs/firmware/.cargo/sim.sh target/riscv32i-unknown-none-elf/debug/firmware`
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-06-13 23:27:52)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 1.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False.
INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-06-13 23:27:52)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 1.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 3).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 2.
INFO:SoCCSRHandler:uart CSR allocated at Location 3.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False
Bus Regions: (3)
rom                 : Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False
sram                : Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False
csr                 : Origin: 0xf0000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (3)
- rom
- sram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (4)
- ctrl           : 0
- identifier_mem : 1
- timer0         : 2
- uart           : 3
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart   : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:SoC Hierarchy:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:
SimSoC
└─── crg (CRG)
└─── bus (SoCBusHandler)
│    └─── _interconnect (InterconnectShared)
│    │    └─── arbiter (Arbiter)
│    │    │    └─── rr (RoundRobin)
│    │    └─── decoder (Decoder)
│    │    └─── timeout (Timeout)
│    │    │    └─── waittimer_0* (WaitTimer)
└─── csr (SoCCSRHandler)
└─── irq (SoCIRQHandler)
└─── ctrl (SoCController)
└─── cpu (VexRiscv)
│    └─── [VexRiscv]
└─── rom (SRAM)
└─── sram (SRAM)
└─── identifier (Identifier)
└─── uart_phy (RS232PHYModel)
└─── uart (UART)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
│    │    └─── eventsourceprocess_1* (EventSourceProcess)
│    └─── tx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
│    └─── rx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
└─── timer0 (Timer)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
└─── csr_bridge (Wishbone2CSR)
│    └─── fsm (FSM)
└─── csr_bankarray (CSRBankArray)
│    └─── csrbank_0* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    └─── sram_0* (SRAM)
│    └─── csrbank_1* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstorage_4* (CSRStorage)
│    └─── csrbank_2* (CSRBank)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstatus_3* (CSRStatus)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstatus_4* (CSRStatus)
│    │    └─── csrstatus_5* (CSRStatus)
└─── csr_interconnect (InterconnectShared)
* : Generated name.
[]: BlackBox.

INFO:SoC:--------------------------------------------------------------------------------
identifier_mem@f0000800: Found memory that's 8 x 37 (but memories aren't documented yet)
make: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware'
mkdir -p modules
make -C modules -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/Makefile
make[1]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules'
mkdir -p xgmii_ethernet
make MOD=xgmii_ethernet -C xgmii_ethernet -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/xgmii_ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/xgmii_ethernet'
cp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so
mkdir -p ethernet
make MOD=ethernet -C ethernet -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/ethernet/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/ethernet'
cp ethernet/ethernet.so ethernet.so
mkdir -p serial2console
make MOD=serial2console -C serial2console -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/serial2console/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/serial2console'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/serial2console'
cp serial2console/serial2console.so serial2console.so
mkdir -p serial2tcp
make MOD=serial2tcp -C serial2tcp -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/serial2tcp/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/serial2tcp'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/serial2tcp'
cp serial2tcp/serial2tcp.so serial2tcp.so
mkdir -p clocker
make MOD=clocker -C clocker -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/clocker/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/clocker'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/clocker'
cp clocker/clocker.so clocker.so
mkdir -p spdeeprom
make MOD=spdeeprom -C spdeeprom -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/spdeeprom/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/spdeeprom'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/spdeeprom'
cp spdeeprom/spdeeprom.so spdeeprom.so
mkdir -p gmii_ethernet
make MOD=gmii_ethernet -C gmii_ethernet -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/gmii_ethernet/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/gmii_ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/gmii_ethernet'
cp gmii_ethernet/gmii_ethernet.so gmii_ethernet.so
mkdir -p jtagremote
make MOD=jtagremote -C jtagremote -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/jtagremote/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/jtagremote'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/jtagremote'
cp jtagremote/jtagremote.so jtagremote.so
make[1]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules'
mkdir -p /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir
cc -c -ggdb -Wall -O3   -o /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir/libdylib.o /home/roby/repos/litex/litex/litex/build/sim/core/libdylib.c
cc -c -ggdb -Wall -O3   -o /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir/modules.o /home/roby/repos/litex/litex/litex/build/sim/core/modules.c
In file included from /home/roby/repos/litex/litex/litex/build/sim/core/modules.c:6:
In function ‘tinydir_readfile’,
    inlined from ‘litex_sim_load_ext_modules’ at /home/roby/repos/litex/litex/litex/build/sim/core/modules.c:68:14:
/home/roby/repos/litex/litex/litex/build/sim/core/tinydir.h:81:25: warning: ‘strcat’ accessing 4097 or more bytes at offsets 0 and 4096 may overlap 1 byte at offset 4096 [-Wrestrict]
   81 | #define _tinydir_strcat strcat
      |                         ^
/home/roby/repos/litex/litex/litex/build/sim/core/tinydir.h:532:9: note: in expansion of macro ‘_tinydir_strcat’
  532 |         _tinydir_strcat(file->path, file->name);
      |         ^~~~~~~~~~~~~~~
cc -c -ggdb -Wall -O3   -o /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir/pads.o /home/roby/repos/litex/litex/litex/build/sim/core/pads.c
cc -c -ggdb -Wall -O3   -o /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir/parse.o /home/roby/repos/litex/litex/litex/build/sim/core/parse.c
cc -c -ggdb -Wall -O3   -o /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir/sim.o /home/roby/repos/litex/litex/litex/build/sim/core/sim.c
verilator -Wno-fatal -O3 --cc /home/roby/repos/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/sim.v  --top-module sim --exe \
        -DPRINTF_COND=0 \
        sim_init.cpp /home/roby/repos/litex/litex/litex/build/sim/core/veril.cpp libdylib.o modules.o pads.o parse.o sim.o \
        --top-module sim \
         \
        -CFLAGS "-ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core" \
        -LDFLAGS "-lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent " \
        --trace \
         \
         \
        --unroll-count 256 \
        --output-split 5000 \
        --output-split-cfuncs 500 \
        --output-split-ctrace 500 \
         \
        -Wno-BLKANDNBLK \
        -Wno-WIDTH \
        -Wno-COMBDLY \
        -Wno-CASEINCOMPLETE \
        --relative-includes
perl: warning: Setting locale failed.
perl: warning: Please check that your locale settings:
        LANGUAGE = "en_US",
        LC_ALL = (unset),
        LC_CTYPE = "C.UTF-8",
        LC_COLLATE = "C",
        LANG = "en_GB.UTF-8"
    are supported and installed on your system.
perl: warning: Falling back to the standard locale ("C").
perl: warning: Setting locale failed.
perl: warning: Please check that your locale settings:
        LANGUAGE = "en_US",
        LC_ALL = (unset),
        LC_CTYPE = "C.UTF-8",
        LC_COLLATE = "C",
        LANG = "en_GB.UTF-8"
    are supported and installed on your system.
perl: warning: Falling back to the standard locale ("C").
- V e r i l a t i o n   R e p o r t: Verilator 5.024 2024-04-05 rev UNKNOWN.REV
- Verilator: Built from 0.742 MB sources in 5 modules, into 1.113 MB in 25 C++ files needing 0.000 MB
- Verilator: Walltime 0.431 s (elab=0.068, cvt=0.255, bld=0.000); cpu 0.000 s on 1 threads; alloced 19.184 MB
make -j -C /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir -f Vsim.mk Vsim
make[1]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir'
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -Os -c -o veril.o /home/roby/repos/litex/litex/litex/build/sim/core/veril.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -Os -c -o sim_init.o ../sim_init.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -c -o verilated.o /usr/share/verilator/include/verilated.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -c -o verilated_threads.o /usr/share/verilator/include/verilated_threads.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -x c++-header Vsim__pch.h -o Vsim__pch.h.fast.gch
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -x c++-header Vsim__pch.h -o Vsim__pch.h.slow.gch
echo "" > Vsim__ALL.verilator_deplist.tmp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim__ConstPool_0.o Vsim__ConstPool_0.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim___024root__Slow.o Vsim___024root__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim___024root__DepSet_h104c642d__0__Slow.o Vsim___024root__DepSet_h104c642d__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim___024root__DepSet_hb1836b75__0__Slow.o Vsim___024root__DepSet_hb1836b75__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_sim__Slow.o Vsim_sim__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_sim__DepSet_h837b84dc__0__Slow.o Vsim_sim__DepSet_h837b84dc__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_sim__DepSet_h40728c06__0__Slow.o Vsim_sim__DepSet_h40728c06__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscv__Slow.o Vsim_VexRiscv__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscv__DepSet_hda50bfa8__0__Slow.o Vsim_VexRiscv__DepSet_hda50bfa8__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscv__DepSet_hda50bfa8__1__Slow.o Vsim_VexRiscv__DepSet_hda50bfa8__1__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscv__DepSet_h9f7c89a9__0__Slow.o Vsim_VexRiscv__DepSet_h9f7c89a9__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim__Syms.o Vsim__Syms.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim__Trace__0__Slow.o Vsim__Trace__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim__TraceDecls__0__Slow.o Vsim__TraceDecls__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim__Trace__1__Slow.o Vsim__Trace__1__Slow.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim.o Vsim.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim___024root__DepSet_h104c642d__0.o Vsim___024root__DepSet_h104c642d__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim___024root__DepSet_hb1836b75__0.o Vsim___024root__DepSet_hb1836b75__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_sim__DepSet_h837b84dc__0.o Vsim_sim__DepSet_h837b84dc__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_sim__DepSet_h40728c06__0.o Vsim_sim__DepSet_h40728c06__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_VexRiscv__DepSet_hda50bfa8__0.o Vsim_VexRiscv__DepSet_hda50bfa8__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_VexRiscv__DepSet_h9f7c89a9__0.o Vsim_VexRiscv__DepSet_h9f7c89a9__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_VexRiscv__DepSet_h9f7c89a9__1.o Vsim_VexRiscv__DepSet_h9f7c89a9__1.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim__Dpi.o Vsim__Dpi.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim__Trace__0.o Vsim__Trace__0.cpp
Archive ar -rcs Vsim__ALL.a Vsim.o Vsim___024root__DepSet_h104c642d__0.o Vsim___024root__DepSet_hb1836b75__0.o Vsim_sim__DepSet_h837b84dc__0.o Vsim_sim__DepSet_h40728c06__0.o Vsim_VexRiscv__DepSet_hda50bfa8__0.o Vsim_VexRiscv__DepSet_h9f7c89a9__0.o Vsim_VexRiscv__DepSet_h9f7c89a9__1.o Vsim__Dpi.o Vsim__Trace__0.o Vsim__ConstPool_0.o Vsim___024root__Slow.o Vsim___024root__DepSet_h104c642d__0__Slow.o Vsim___024root__DepSet_hb1836b75__0__Slow.o Vsim_sim__Slow.o Vsim_sim__DepSet_h837b84dc__0__Slow.o Vsim_sim__DepSet_h40728c06__0__Slow.o Vsim_VexRiscv__Slow.o Vsim_VexRiscv__DepSet_hda50bfa8__0__Slow.o Vsim_VexRiscv__DepSet_hda50bfa8__1__Slow.o Vsim_VexRiscv__DepSet_h9f7c89a9__0__Slow.o Vsim__Syms.o Vsim__Trace__0__Slow.o Vsim__TraceDecls__0__Slow.o Vsim__Trace__1__Slow.o
g++    veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o verilated_threads.o Vsim__ALL.a   libdylib.o modules.o pads.o parse.o sim.o -lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent  -pthread -lpthread -latomic   -o Vsim
rm Vsim__ALL.verilator_deplist.tmp
make[1]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir'
make: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware'

[serial2console] loaded (0x60918c8be2f0)
[clocker] loaded
[xgmii_ethernet] loaded (0x60918c8be2f0)
[gmii_ethernet] loaded (0x60918c8be2f0)
[jtagremote] loaded (0x60918c8be2f0)
[ethernet] loaded (0x60918c8be2f0)
[serial2tcp] loaded (0x60918c8be2f0)
[spdeeprom] loaded (addr = 0x0)
[clocker] sys_clk: freq_hz=1000000, phase_deg=0
hello
hello
hello
hello
hello
hello
hello
hello
hello
hello
hello
hello

--ram-init

set -e
riscv64-elf-objcopy $1 -O binary $1.bin
litex_sim --output-dir=target/litex_sim --cpu-type=vexriscv --rom-init=$1.bin --no-compile-software --csr-csv "csr.csv"

output:

(.venv) [roby@thonkpad firmware]$ cargo run
   Compiling litex-pac v0.1.0 (/home/roby/repos/colorlight-litex-rs/litex-pac)
   Compiling firmware v0.1.0 (/home/roby/repos/colorlight-litex-rs/firmware)
    Finished dev [unoptimized + debuginfo] target(s) in 0.53s
     Running `/home/roby/repos/colorlight-litex-rs/firmware/.cargo/sim.sh target/riscv32i-unknown-none-elf/debug/firmware`
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-06-13 23:29:16)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 1.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False.
INFO:SoC:CPU vexriscv overriding sram mapping from 0x01000000 to 0x10000000.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoC:        __   _ __      _  __  
INFO:SoC:       / /  (_) /____ | |/_/  
INFO:SoC:      / /__/ / __/ -_)>  <    
INFO:SoC:     /____/_/\__/\__/_/|_|  
INFO:SoC:  Build your hardware, easily!
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Creating SoC... (2024-06-13 23:29:16)
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:FPGA device : SIM.
INFO:SoC:System clock: 1.000MHz.
INFO:SoCBusHandler:Creating Bus Handler...
INFO:SoCBusHandler:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoCBusHandler:Adding reserved Bus Regions...
INFO:SoCBusHandler:Bus Handler created.
INFO:SoCCSRHandler:Creating CSR Handler...
INFO:SoCCSRHandler:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoCCSRHandler:Adding reserved CSRs...
INFO:SoCCSRHandler:CSR Handler created.
INFO:SoCIRQHandler:Creating IRQ Handler...
INFO:SoCIRQHandler:IRQ Handler (up to 32 Locations).
INFO:SoCIRQHandler:Adding reserved IRQs...
INFO:SoCIRQHandler:IRQ Handler created.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Initial SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
INFO:SoC:IRQ Handler (up to 32 Locations).
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Controller ctrl added.
INFO:SoC:CPU vexriscv added.
INFO:SoC:CPU vexriscv adding IO Region 0 at 0x80000000 (Size: 0x80000000).
INFO:SoCBusHandler:io0 Region added at Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False.
INFO:SoC:CPU vexriscv setting reset address to 0x00000000.
INFO:SoC:CPU vexriscv adding Bus Master(s).
INFO:SoCBusHandler:cpu_bus0 added as Bus Master.
INFO:SoCBusHandler:cpu_bus1 added as Bus Master.
INFO:SoC:CPU vexriscv adding Interrupt(s).
INFO:SoC:CPU vexriscv adding SoC components.
INFO:SoCBusHandler:rom Region added at Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:rom added as Bus Slave.
INFO:SoC:RAM rom added Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram Region added at Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCBusHandler:sram added as Bus Slave.
INFO:SoC:RAM sram added Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False.
INFO:SoCIRQHandler:uart IRQ allocated at Location 0.
INFO:SoCIRQHandler:timer0 IRQ allocated at Location 1.
INFO:SoC:CSR Bridge csr added.
INFO:SoCBusHandler:csr Region added at Origin: 0xf0000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False.
INFO:SoCBusHandler:csr added as Bus Slave.
INFO:SoCCSRHandler:csr added as CSR Master.
INFO:SoCBusHandler:Interconnect: InterconnectShared (2 <-> 3).
INFO:SoCCSRHandler:ctrl CSR allocated at Location 0.
INFO:SoCCSRHandler:identifier_mem CSR allocated at Location 1.
INFO:SoCCSRHandler:timer0 CSR allocated at Location 2.
INFO:SoCCSRHandler:uart CSR allocated at Location 3.
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:Finalized SoC:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:32-bit wishbone Bus, 4.0GiB Address Space.
IO Regions: (1)
io0                 : Origin: 0x80000000, Size: 0x80000000, Mode:  RW, Cached: False, Linker: False
Bus Regions: (3)
rom                 : Origin: 0x00000000, Size: 0x00020000, Mode:  RX, Cached:  True, Linker: False
sram                : Origin: 0x10000000, Size: 0x00002000, Mode: RWX, Cached:  True, Linker: False
csr                 : Origin: 0xf0000000, Size: 0x00010000, Mode:  RW, Cached: False, Linker: False
Bus Masters: (2)
- cpu_bus0
- cpu_bus1
Bus Slaves: (3)
- rom
- sram
- csr
INFO:SoC:32-bit CSR Bus, 32-bit Aligned, 16.0KiB Address Space, 2048B Paging, big Ordering (Up to 32 Locations).
CSR Locations: (4)
- ctrl           : 0
- identifier_mem : 1
- timer0         : 2
- uart           : 3
INFO:SoC:IRQ Handler (up to 32 Locations).
IRQ Locations: (2)
- uart   : 0
- timer0 : 1
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:SoC Hierarchy:
INFO:SoC:--------------------------------------------------------------------------------
INFO:SoC:
SimSoC
└─── crg (CRG)
└─── bus (SoCBusHandler)
│    └─── _interconnect (InterconnectShared)
│    │    └─── arbiter (Arbiter)
│    │    │    └─── rr (RoundRobin)
│    │    └─── decoder (Decoder)
│    │    └─── timeout (Timeout)
│    │    │    └─── waittimer_0* (WaitTimer)
└─── csr (SoCCSRHandler)
└─── irq (SoCIRQHandler)
└─── ctrl (SoCController)
└─── cpu (VexRiscv)
│    └─── [VexRiscv]
└─── rom (SRAM)
└─── sram (SRAM)
└─── identifier (Identifier)
└─── uart_phy (RS232PHYModel)
└─── uart (UART)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
│    │    └─── eventsourceprocess_1* (EventSourceProcess)
│    └─── tx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
│    └─── rx_fifo (SyncFIFO)
│    │    └─── fifo (SyncFIFOBuffered)
│    │    │    └─── fifo (SyncFIFO)
└─── timer0 (Timer)
│    └─── ev (EventManager)
│    │    └─── eventsourceprocess_0* (EventSourceProcess)
└─── csr_bridge (Wishbone2CSR)
│    └─── fsm (FSM)
└─── csr_bankarray (CSRBankArray)
│    └─── csrbank_0* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    └─── sram_0* (SRAM)
│    └─── csrbank_1* (CSRBank)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstorage_1* (CSRStorage)
│    │    └─── csrstorage_2* (CSRStorage)
│    │    └─── csrstorage_3* (CSRStorage)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstorage_4* (CSRStorage)
│    └─── csrbank_2* (CSRBank)
│    │    └─── csrstatus_0* (CSRStatus)
│    │    └─── csrstatus_1* (CSRStatus)
│    │    └─── csrstatus_2* (CSRStatus)
│    │    └─── csrstatus_3* (CSRStatus)
│    │    └─── csrstorage_0* (CSRStorage)
│    │    └─── csrstatus_4* (CSRStatus)
│    │    └─── csrstatus_5* (CSRStatus)
└─── csr_interconnect (InterconnectShared)
* : Generated name.
[]: BlackBox.

INFO:SoC:--------------------------------------------------------------------------------
identifier_mem@f0000800: Found memory that's 8 x 37 (but memories aren't documented yet)
make: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware'
mkdir -p modules
make -C modules -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/Makefile
make[1]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules'
mkdir -p xgmii_ethernet
make MOD=xgmii_ethernet -C xgmii_ethernet -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/xgmii_ethernet/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/xgmii_ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/xgmii_ethernet'
cp xgmii_ethernet/xgmii_ethernet.so xgmii_ethernet.so
mkdir -p ethernet
make MOD=ethernet -C ethernet -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/ethernet/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/ethernet'
cp ethernet/ethernet.so ethernet.so
mkdir -p serial2console
make MOD=serial2console -C serial2console -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/serial2console/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/serial2console'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/serial2console'
cp serial2console/serial2console.so serial2console.so
mkdir -p serial2tcp
make MOD=serial2tcp -C serial2tcp -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/serial2tcp/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/serial2tcp'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/serial2tcp'
cp serial2tcp/serial2tcp.so serial2tcp.so
mkdir -p clocker
make MOD=clocker -C clocker -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/clocker/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/clocker'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/clocker'
cp clocker/clocker.so clocker.so
mkdir -p spdeeprom
make MOD=spdeeprom -C spdeeprom -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/spdeeprom/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/spdeeprom'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/spdeeprom'
cp spdeeprom/spdeeprom.so spdeeprom.so
mkdir -p gmii_ethernet
make MOD=gmii_ethernet -C gmii_ethernet -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/gmii_ethernet/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/gmii_ethernet'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/gmii_ethernet'
cp gmii_ethernet/gmii_ethernet.so gmii_ethernet.so
mkdir -p jtagremote
make MOD=jtagremote -C jtagremote -f /home/roby/repos/litex/litex/litex/build/sim/core/modules/jtagremote/Makefile
make[2]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/jtagremote'
make[2]: Nothing to be done for 'all'.
make[2]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules/jtagremote'
cp jtagremote/jtagremote.so jtagremote.so
make[1]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/modules'
mkdir -p /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir
cc -c -ggdb -Wall -O3   -o /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir/libdylib.o /home/roby/repos/litex/litex/litex/build/sim/core/libdylib.c
cc -c -ggdb -Wall -O3   -o /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir/modules.o /home/roby/repos/litex/litex/litex/build/sim/core/modules.c
In file included from /home/roby/repos/litex/litex/litex/build/sim/core/modules.c:6:
In function ‘tinydir_readfile’,
    inlined from ‘litex_sim_load_ext_modules’ at /home/roby/repos/litex/litex/litex/build/sim/core/modules.c:68:14:
/home/roby/repos/litex/litex/litex/build/sim/core/tinydir.h:81:25: warning: ‘strcat’ accessing 4097 or more bytes at offsets 0 and 4096 may overlap 1 byte at offset 4096 [-Wrestrict]
   81 | #define _tinydir_strcat strcat
      |                         ^
/home/roby/repos/litex/litex/litex/build/sim/core/tinydir.h:532:9: note: in expansion of macro ‘_tinydir_strcat’
  532 |         _tinydir_strcat(file->path, file->name);
      |         ^~~~~~~~~~~~~~~
cc -c -ggdb -Wall -O3   -o /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir/pads.o /home/roby/repos/litex/litex/litex/build/sim/core/pads.c
cc -c -ggdb -Wall -O3   -o /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir/parse.o /home/roby/repos/litex/litex/litex/build/sim/core/parse.c
cc -c -ggdb -Wall -O3   -o /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir/sim.o /home/roby/repos/litex/litex/litex/build/sim/core/sim.c
verilator -Wno-fatal -O3 --cc /home/roby/repos/litex/pythondata-cpu-vexriscv/pythondata_cpu_vexriscv/verilog/VexRiscv.v --cc /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/sim.v  --top-module sim --exe \
        -DPRINTF_COND=0 \
        sim_init.cpp /home/roby/repos/litex/litex/litex/build/sim/core/veril.cpp libdylib.o modules.o pads.o parse.o sim.o \
        --top-module sim \
         \
        -CFLAGS "-ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core" \
        -LDFLAGS "-lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent " \
        --trace \
         \
         \
        --unroll-count 256 \
        --output-split 5000 \
        --output-split-cfuncs 500 \
        --output-split-ctrace 500 \
         \
        -Wno-BLKANDNBLK \
        -Wno-WIDTH \
        -Wno-COMBDLY \
        -Wno-CASEINCOMPLETE \
        --relative-includes
perl: warning: Setting locale failed.
perl: warning: Please check that your locale settings:
        LANGUAGE = "en_US",
        LC_ALL = (unset),
        LC_CTYPE = "C.UTF-8",
        LC_COLLATE = "C",
        LANG = "en_GB.UTF-8"
    are supported and installed on your system.
perl: warning: Falling back to the standard locale ("C").
perl: warning: Setting locale failed.
perl: warning: Please check that your locale settings:
        LANGUAGE = "en_US",
        LC_ALL = (unset),
        LC_CTYPE = "C.UTF-8",
        LC_COLLATE = "C",
        LANG = "en_GB.UTF-8"
    are supported and installed on your system.
perl: warning: Falling back to the standard locale ("C").
- V e r i l a t i o n   R e p o r t: Verilator 5.024 2024-04-05 rev UNKNOWN.REV
- Verilator: Built from 0.742 MB sources in 5 modules, into 1.113 MB in 25 C++ files needing 0.000 MB
- Verilator: Walltime 0.420 s (elab=0.065, cvt=0.251, bld=0.000); cpu 0.000 s on 1 threads; alloced 19.176 MB
make -j -C /home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir -f Vsim.mk Vsim
make[1]: Entering directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir'
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -Os -c -o veril.o /home/roby/repos/litex/litex/litex/build/sim/core/veril.cpp
g++  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -Os -c -o sim_init.o ../sim_init.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -c -o verilated.o /usr/share/verilator/include/verilated.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -c -o verilated_dpi.o /usr/share/verilator/include/verilated_dpi.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -c -o verilated_vcd_c.o /usr/share/verilator/include/verilated_vcd_c.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -c -o verilated_threads.o /usr/share/verilator/include/verilated_threads.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -x c++-header Vsim__pch.h -o Vsim__pch.h.fast.gch
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -x c++-header Vsim__pch.h -o Vsim__pch.h.slow.gch
echo "" > Vsim__ALL.verilator_deplist.tmp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim.o Vsim.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim___024root__DepSet_h104c642d__0.o Vsim___024root__DepSet_h104c642d__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim___024root__DepSet_hb1836b75__0.o Vsim___024root__DepSet_hb1836b75__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_sim__DepSet_h837b84dc__0.o Vsim_sim__DepSet_h837b84dc__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_sim__DepSet_h40728c06__0.o Vsim_sim__DepSet_h40728c06__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_VexRiscv__DepSet_hda50bfa8__0.o Vsim_VexRiscv__DepSet_hda50bfa8__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_VexRiscv__DepSet_h9f7c89a9__0.o Vsim_VexRiscv__DepSet_h9f7c89a9__0.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim_VexRiscv__DepSet_h9f7c89a9__1.o Vsim_VexRiscv__DepSet_h9f7c89a9__1.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim__Dpi.o Vsim__Dpi.cpp
g++ -Os  -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.fast -c -o Vsim__Trace__0.o Vsim__Trace__0.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim__ConstPool_0.o Vsim__ConstPool_0.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim___024root__Slow.o Vsim___024root__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim___024root__DepSet_h104c642d__0__Slow.o Vsim___024root__DepSet_h104c642d__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim___024root__DepSet_hb1836b75__0__Slow.o Vsim___024root__DepSet_hb1836b75__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_sim__Slow.o Vsim_sim__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_sim__DepSet_h837b84dc__0__Slow.o Vsim_sim__DepSet_h837b84dc__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_sim__DepSet_h40728c06__0__Slow.o Vsim_sim__DepSet_h40728c06__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscv__Slow.o Vsim_VexRiscv__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscv__DepSet_hda50bfa8__0__Slow.o Vsim_VexRiscv__DepSet_hda50bfa8__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscv__DepSet_hda50bfa8__1__Slow.o Vsim_VexRiscv__DepSet_hda50bfa8__1__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim_VexRiscv__DepSet_h9f7c89a9__0__Slow.o Vsim_VexRiscv__DepSet_h9f7c89a9__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim__Syms.o Vsim__Syms.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim__Trace__0__Slow.o Vsim__Trace__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim__TraceDecls__0__Slow.o Vsim__TraceDecls__0__Slow.cpp
g++   -I.  -MMD -I/usr/share/verilator/include -I/usr/share/verilator/include/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TRACE=1 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=1 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable    -ggdb -Wall -O3   -I/home/roby/repos/litex/litex/litex/build/sim/core   -include Vsim__pch.h.slow -c -o Vsim__Trace__1__Slow.o Vsim__Trace__1__Slow.cpp
Archive ar -rcs Vsim__ALL.a Vsim.o Vsim___024root__DepSet_h104c642d__0.o Vsim___024root__DepSet_hb1836b75__0.o Vsim_sim__DepSet_h837b84dc__0.o Vsim_sim__DepSet_h40728c06__0.o Vsim_VexRiscv__DepSet_hda50bfa8__0.o Vsim_VexRiscv__DepSet_h9f7c89a9__0.o Vsim_VexRiscv__DepSet_h9f7c89a9__1.o Vsim__Dpi.o Vsim__Trace__0.o Vsim__ConstPool_0.o Vsim___024root__Slow.o Vsim___024root__DepSet_h104c642d__0__Slow.o Vsim___024root__DepSet_hb1836b75__0__Slow.o Vsim_sim__Slow.o Vsim_sim__DepSet_h837b84dc__0__Slow.o Vsim_sim__DepSet_h40728c06__0__Slow.o Vsim_VexRiscv__Slow.o Vsim_VexRiscv__DepSet_hda50bfa8__0__Slow.o Vsim_VexRiscv__DepSet_hda50bfa8__1__Slow.o Vsim_VexRiscv__DepSet_h9f7c89a9__0__Slow.o Vsim__Syms.o Vsim__Trace__0__Slow.o Vsim__TraceDecls__0__Slow.o Vsim__Trace__1__Slow.o
g++    veril.o sim_init.o verilated.o verilated_dpi.o verilated_vcd_c.o verilated_threads.o Vsim__ALL.a   libdylib.o modules.o pads.o parse.o sim.o -lpthread -Wl,--no-as-needed -ljson-c -lz -lm -lstdc++ -Wl,--no-as-needed -ldl -levent  -pthread -lpthread -latomic   -o Vsim
rm Vsim__ALL.verilator_deplist.tmp
make[1]: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware/obj_dir'
make: Leaving directory '/home/roby/repos/colorlight-litex-rs/firmware/target/litex_sim/gateware'

[serial2console] loaded (0x5911855162f0)
[clocker] loaded
[xgmii_ethernet] loaded (0x5911855162f0)
[gmii_ethernet] loaded (0x5911855162f0)
[jtagremote] loaded (0x5911855162f0)
[ethernet] loaded (0x5911855162f0)
[serial2tcp] loaded (0x5911855162f0)
[spdeeprom] loaded (addr = 0x0)
[clocker] sys_clk: freq_hz=1000000, phase_deg=0

In rust, the HAL & PAC auto generate memory.x which maps the regions:

MEMORY {
	rom : ORIGIN = 0x00000000, LENGTH = 0x00008000
	sram : ORIGIN = 0x10000000, LENGTH = 0x00002000
	main_ram : ORIGIN = 0x40000000, LENGTH = 0x00004000
	bootrom : ORIGIN = 0x20000000, LENGTH = 0x00000400
	csr : ORIGIN = 0xf0000000, LENGTH = 0x00010000
}

REGION_ALIAS("REGION_TEXT", rom);
REGION_ALIAS("REGION_RODATA", rom);
REGION_ALIAS("REGION_DATA", sram);
REGION_ALIAS("REGION_BSS", sram);
REGION_ALIAS("REGION_HEAP", sram);
REGION_ALIAS("REGION_STACK", sram);

/* CPU reset location. */
_stext = 0x000000;

How can I provie more inorder to find out whats wrongs here?
Thank you .

AndrewD · 2024-07-08T20:28:21Z

`MEMORY {
rom : ORIGIN = 0x00000000, LENGTH = 0x00008000
sram : ORIGIN = 0x10000000, LENGTH = 0x00002000
main_ram : ORIGIN = 0x40000000, LENGTH = 0x00004000
bootrom : ORIGIN = 0x20000000, LENGTH = 0x00000400
csr : ORIGIN = 0xf0000000, LENGTH = 0x00010000
}

REGION_ALIAS("REGION_TEXT", rom);
REGION_ALIAS("REGION_RODATA", rom);
REGION_ALIAS("REGION_DATA", sram);`

The problem is that you code is linked into rom. Edit memory.x to place code in main_ram as follows:
REGION_ALIAS("REGION_TEXT", main_ram); REGION_ALIAS("REGION_RODATA", main_ram); REGION_ALIAS("REGION_DATA", sram);

Then build your binary to load to main ram.

I don't think the reset address is used when you load this way.

It would be great if you can document the steps you followed to get to here as you are very close to a working solution: from a quick search I suspect you used svd2rust and possibly followed an online write-up I found, but it would be great to get confirmation.

I'm interested in reproducing this and adding some info to the wiki.

roby2014 · 2024-09-26T20:32:19Z

hi @enjoy-digital and @AndrewD .
updates on this (as described in the discord thread:

i load soc with python3 soc.py --load --no-compile-software --memory-x "../litex-pac/memory.x"
i change memory.x (main_ram for text, rodata and data and remove _stext = 0x000000;)
i flash firmware with litex_term --kernel firmware.bin /dev/ttyUSB0
nothing happens
i load soc again with same command from step 1, i see expected result (hello world)
everytime i load firmware with command from step 3 , everything works fine

is this expected? shouldnt it work at the first time i flash the firmware?

keeping it here for future reference

AndrewD mentioned this issue Apr 20, 2024

Loading binary hangs up #1933

Open

roby2014 mentioned this issue Apr 20, 2024

No output after "Liftoff!" on NexysA7/CVA6 #1668

Open

roby2014 changed the title ~~Trying to interact with UART via Rust binary~~ Trying to interact with UART via Rust binary (stuck at liftoff) Apr 21, 2024

enjoy-digital added question third-party-bug answered-waiting-feedback labels Jun 13, 2024

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Trying to interact with UART via Rust binary (stuck at liftoff) #1935

Trying to interact with UART via Rust binary (stuck at liftoff) #1935

roby2014 commented Apr 20, 2024

AndrewD commented Apr 20, 2024

roby2014 commented Apr 21, 2024 •

edited

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enjoy-digital commented Jun 13, 2024

roby2014 commented Jun 13, 2024 •

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AndrewD commented Jul 8, 2024

roby2014 commented Sep 26, 2024 •

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Trying to interact with UART via Rust binary (stuck at liftoff) #1935

Trying to interact with UART via Rust binary (stuck at liftoff) #1935

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roby2014 commented Apr 20, 2024

AndrewD commented Apr 20, 2024

roby2014 commented Apr 21, 2024 • edited Loading

enjoy-digital commented Jun 13, 2024

roby2014 commented Jun 13, 2024 • edited Loading

--rom-init

--ram-init

AndrewD commented Jul 8, 2024

roby2014 commented Sep 26, 2024 • edited Loading

roby2014 commented Apr 21, 2024 •

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roby2014 commented Jun 13, 2024 •

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roby2014 commented Sep 26, 2024 •

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