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fix clock usage in timer driver for idf 5 #441
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#[cfg(not(esp_idf_version_major = "4"))] | ||
#[allow(clippy::upper_case_acronyms)] | ||
pub(crate) enum ClockSource { |
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Nit: why pub(crate)
?
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Tbh i dont like our current clocktree api design, or lag of it. So this is more of a stopgab solution, till we have a general better api for that sort of stuff. Thats why i didn't want to expose it into public api.
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I meant why is it with a crate visibility and not private, but then again - just a nit.
src/timer.rs
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} | ||
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#[cfg(not(esp_idf_version_major = "4"))] | ||
impl Default for ClockSource { |
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Nit: you can replace all of this with just #[default]
above, because for each MCU you end up with exactly two members of the enum, where the XTAL
member should always be the non-default one.
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done
Just two nits. I think you can merge without addressing these either, as they are nits. |
Newer esp's (c2/h2/c6) don't use the apb clock as a default clock for the timer. They use different variants of the pll clock. Furthermore the general assumption that the xtal clock is always 40Mhz is not correct. This PR includes fixes for the TimeDriver in this respect.
closes #426