feat(gpio): add a dump API to dump IO configurations

Closes #12176
espressif · Oct 12, 2023 · 321f628 · 321f628
1 parent 4356ded
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Showing 17 changed files with 557 additions and 13 deletions.
diff --git a/components/driver/gpio/gpio.c b/components/driver/gpio/gpio.c
@@ -22,6 +22,7 @@
 #include "esp_check.h"
 #include "hal/gpio_hal.h"
 #include "esp_rom_gpio.h"
+#include "esp_private/esp_gpio_reserve.h"
 
 #if (SOC_RTCIO_PIN_COUNT > 0)
 #include "hal/rtc_io_hal.h"
@@ -1006,3 +1007,45 @@ esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num)
     return ESP_OK;
 }
 #endif // SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
+
+esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask)
+{
+    ESP_RETURN_ON_FALSE(out_stream, ESP_ERR_INVALID_ARG, GPIO_TAG, "out_stream error");
+    ESP_RETURN_ON_FALSE(!(io_bit_mask & ~SOC_GPIO_VALID_GPIO_MASK), ESP_ERR_INVALID_ARG, GPIO_TAG, "io_bit_mask error");
+
+    fprintf(out_stream, "================IO DUMP Start================\n");
+    while (io_bit_mask) {
+        uint32_t gpio_num = __builtin_ffsll(io_bit_mask) - 1;
+        io_bit_mask &= ~(1ULL << gpio_num);
+
+        bool pu, pd, ie, oe, od, slp_sel;
+        uint32_t drv, fun_sel, sig_out;
+        gpio_hal_get_io_config(gpio_context.gpio_hal, gpio_num, &pu, &pd, &ie, &oe, &od, &drv, &fun_sel, &sig_out, &slp_sel);
+
+        fprintf(out_stream, "IO[%"PRIu32"]%s -\n", gpio_num, esp_gpio_is_pin_reserved(gpio_num) ? " **RESERVED**" : "");
+        fprintf(out_stream, "  Pullup: %d, Pulldown: %d, DriveCap: %"PRIu32"\n", pu, pd, drv);
+        fprintf(out_stream, "  InputEn: %d, OutputEn: %d, OpenDrain: %d\n", ie, oe, od);
+        fprintf(out_stream, "  FuncSel: %"PRIu32" (%s)\n", fun_sel, (fun_sel == PIN_FUNC_GPIO) ? "GPIO" : "IOMUX");
+        if (oe && fun_sel == PIN_FUNC_GPIO) {
+            fprintf(out_stream, "  GPIO Matrix SigOut ID: %"PRIu32"%s\n", sig_out, (sig_out == SIG_GPIO_OUT_IDX) ? " (simple GPIO output)" : "");
+        }
+        if (ie && fun_sel == PIN_FUNC_GPIO) {
+            uint32_t cnt = 0;
+            fprintf(out_stream, "  GPIO Matrix SigIn ID:");
+            for (int i = 0; i < SIG_GPIO_OUT_IDX; i++) {
+                if (gpio_hal_get_in_signal_connected_io(gpio_context.gpio_hal, i) == gpio_num) {
+                    cnt++;
+                    fprintf(out_stream, " %d", i);
+                }
+            }
+            if (cnt == 0) {
+                fprintf(out_stream, " (simple GPIO input)");
+            }
+            fprintf(out_stream, "\n");
+        }
+        fprintf(out_stream, "  SleepSelEn: %d\n", slp_sel);
+        fprintf(out_stream, "\n");
+    }
+    fprintf(out_stream, "=================IO DUMP End==================\n");
+    return ESP_OK;
+}
diff --git a/components/driver/gpio/include/driver/gpio.h b/components/driver/gpio/include/driver/gpio.h
@@ -1,11 +1,12 @@
 /*
- * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
 
 #pragma once
 
+#include <stdio.h>
 #include <stdbool.h>
 #include "sdkconfig.h"
 #include "esp_err.h"
@@ -543,7 +544,19 @@ esp_err_t gpio_deep_sleep_wakeup_enable(gpio_num_t gpio_num, gpio_int_type_t int
  */
 esp_err_t gpio_deep_sleep_wakeup_disable(gpio_num_t gpio_num);
 
-#endif
+#endif //SOC_GPIO_SUPPORT_DEEPSLEEP_WAKEUP
+
+/**
+ * @brief Dump IO configuration information to console
+ *
+ * @param out_stream IO stream (e.g. stdout)
+ * @param io_bit_mask IO pin bit mask, each bit maps to an IO
+ *
+ * @return
+ *    - ESP_OK Success
+ *    - ESP_ERR_INVALID_ARG Parameter error
+ */
+esp_err_t gpio_dump_io_configuration(FILE *out_stream, uint64_t io_bit_mask);
 
 #ifdef __cplusplus
 }

diff --git a/components/hal/esp32/include/hal/gpio_ll.h b/components/hal/esp32/include/hal/gpio_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -39,6 +39,39 @@ extern const uint8_t GPIO_PIN_MUX_REG_OFFSET[SOC_GPIO_PIN_COUNT];
 #define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(3))
 #define GPIO_LL_SDIO_EXT_INTR_ENA     (BIT(4))
 
+/**
+ * @brief Get the configuration for an IO
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ * @param pu Pull-up enabled or not
+ * @param pd Pull-down enabled or not
+ * @param ie Input enabled or not
+ * @param oe Output enabled or not
+ * @param od Open-drain enabled or not
+ * @param drv Drive strength value
+ * @param fun_sel IOMUX function selection value
+ * @param sig_out Outputting peripheral signal index
+ * @param slp_sel Pin sleep mode enabled or not
+ */
+static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
+                                         bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
+                                         uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
+{
+    uint32_t bit_shift = (gpio_num < 32) ? gpio_num : (gpio_num - 32);
+    uint32_t bit_mask = 1 << bit_shift;
+    uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
+    *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
+    *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
+    *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
+    *oe = (((gpio_num < 32) ? hw->enable : hw->enable1.val) & bit_mask) >> bit_shift;
+    *od = hw->pin[gpio_num].pad_driver;
+    *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
+    *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
+    *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
+    *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
+}
+
 /**
   * @brief Enable pull-up on GPIO.
   *
@@ -669,6 +702,23 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
     gpio_ll_func_sel(hw, gpio_num, func);
 }
 
+/**
+ * @brief Get the GPIO number that is routed to the input peripheral signal through GPIO matrix.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param in_sig_idx Peripheral signal index (tagged as input attribute).
+ *
+ * @return
+ *    - -1     Signal bypassed GPIO matrix
+ *    - Others GPIO number
+ */
+static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx)
+{
+    typeof(hw->func_in_sel_cfg[in_sig_idx]) reg;
+    reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
+    return (reg.sig_in_sel ? reg.func_sel : -1);
+}
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/components/hal/esp32c2/include/hal/gpio_ll.h b/components/hal/esp32c2/include/hal/gpio_ll.h
@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -31,6 +31,39 @@ extern "C" {
 
 #define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(0))
 #define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+
+/**
+ * @brief Get the configuration for an IO
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ * @param pu Pull-up enabled or not
+ * @param pd Pull-down enabled or not
+ * @param ie Input enabled or not
+ * @param oe Output enabled or not
+ * @param od Open-drain enabled or not
+ * @param drv Drive strength value
+ * @param fun_sel IOMUX function selection value
+ * @param sig_out Outputting peripheral signal index
+ * @param slp_sel Pin sleep mode enabled or not
+ */
+static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
+                                         bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
+                                         uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
+{
+    uint32_t bit_mask = 1 << gpio_num;
+    uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
+    *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
+    *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
+    *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
+    *oe = (hw->enable.val & bit_mask) >> gpio_num;
+    *od = hw->pin[gpio_num].pad_driver;
+    *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
+    *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
+    *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
+    *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
+}
+
 /**
   * @brief Enable pull-up on GPIO.
   *
@@ -475,6 +508,23 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
     gpio_ll_func_sel(hw, gpio_num, func);
 }
 
+/**
+ * @brief Get the GPIO number that is routed to the input peripheral signal through GPIO matrix.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param in_sig_idx Peripheral signal index (tagged as input attribute).
+ *
+ * @return
+ *    - -1     Signal bypassed GPIO matrix
+ *    - Others GPIO number
+ */
+static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx)
+{
+    gpio_func_in_sel_cfg_reg_t reg;
+    reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
+    return (reg.sig_in_sel ? reg.func_sel : -1);
+}
+
 /**
   * @brief Force hold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads.
   * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.

diff --git a/components/hal/esp32c3/include/hal/gpio_ll.h b/components/hal/esp32c3/include/hal/gpio_ll.h
@@ -33,6 +33,39 @@ extern "C" {
 
 #define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(0))
 #define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+
+/**
+ * @brief Get the configuration for an IO
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ * @param pu Pull-up enabled or not
+ * @param pd Pull-down enabled or not
+ * @param ie Input enabled or not
+ * @param oe Output enabled or not
+ * @param od Open-drain enabled or not
+ * @param drv Drive strength value
+ * @param fun_sel IOMUX function selection value
+ * @param sig_out Outputting peripheral signal index
+ * @param slp_sel Pin sleep mode enabled or not
+ */
+static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
+                                         bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
+                                         uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
+{
+    uint32_t bit_mask = 1 << gpio_num;
+    uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
+    *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
+    *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
+    *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
+    *oe = (hw->enable.val & bit_mask) >> gpio_num;
+    *od = hw->pin[gpio_num].pad_driver;
+    *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
+    *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
+    *sig_out = hw->func_out_sel_cfg[gpio_num].func_sel;
+    *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
+}
+
 /**
   * @brief Enable pull-up on GPIO.
   *
@@ -491,6 +524,23 @@ static inline void gpio_ll_iomux_out(gpio_dev_t *hw, uint8_t gpio_num, int func,
     gpio_ll_func_sel(hw, gpio_num, func);
 }
 
+/**
+ * @brief Get the GPIO number that is routed to the input peripheral signal through GPIO matrix.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param in_sig_idx Peripheral signal index (tagged as input attribute).
+ *
+ * @return
+ *    - -1     Signal bypassed GPIO matrix
+ *    - Others GPIO number
+ */
+static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx)
+{
+    typeof(hw->func_in_sel_cfg[in_sig_idx]) reg;
+    reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
+    return (reg.sig_in_sel ? reg.func_sel : -1);
+}
+
 /**
   * @brief Force hold all digital(VDD3P3_CPU) and rtc(VDD3P3_RTC) gpio pads.
   * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.

diff --git a/components/hal/esp32c6/include/hal/gpio_ll.h b/components/hal/esp32c6/include/hal/gpio_ll.h
@@ -38,6 +38,39 @@ extern "C" {
 
 #define GPIO_LL_PRO_CPU_INTR_ENA      (BIT(0))
 #define GPIO_LL_PRO_CPU_NMI_INTR_ENA  (BIT(1))
+
+/**
+ * @brief Get the configuration for an IO
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param gpio_num GPIO number
+ * @param pu Pull-up enabled or not
+ * @param pd Pull-down enabled or not
+ * @param ie Input enabled or not
+ * @param oe Output enabled or not
+ * @param od Open-drain enabled or not
+ * @param drv Drive strength value
+ * @param fun_sel IOMUX function selection value
+ * @param sig_out Outputting peripheral signal index
+ * @param slp_sel Pin sleep mode enabled or not
+ */
+static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
+                                         bool *pu, bool *pd, bool *ie, bool *oe, bool *od, uint32_t *drv,
+                                         uint32_t *fun_sel, uint32_t *sig_out, bool *slp_sel)
+{
+    uint32_t bit_mask = 1 << gpio_num;
+    uint32_t iomux_reg_val = REG_READ(GPIO_PIN_MUX_REG[gpio_num]);
+    *pu = (iomux_reg_val & FUN_PU_M) >> FUN_PU_S;
+    *pd = (iomux_reg_val & FUN_PD_M) >> FUN_PD_S;
+    *ie = (iomux_reg_val & FUN_IE_M) >> FUN_IE_S;
+    *oe = (hw->enable.val & bit_mask) >> gpio_num;
+    *od = hw->pin[gpio_num].pad_driver;
+    *drv = (iomux_reg_val & FUN_DRV_M) >> FUN_DRV_S;
+    *fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
+    *sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
+    *slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
+}
+
 /**
   * @brief Enable pull-up on GPIO.
   *
@@ -478,6 +511,23 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
     }
 }
 
+/**
+ * @brief Get the GPIO number that is routed to the input peripheral signal through GPIO matrix.
+ *
+ * @param hw Peripheral GPIO hardware instance address.
+ * @param in_sig_idx Peripheral signal index (tagged as input attribute).
+ *
+ * @return
+ *    - -1     Signal bypassed GPIO matrix
+ *    - Others GPIO number
+ */
+static inline int gpio_ll_get_in_signal_connected_io(gpio_dev_t *hw, uint32_t in_sig_idx)
+{
+    gpio_func_in_sel_cfg_reg_t reg;
+    reg.val = hw->func_in_sel_cfg[in_sig_idx].val;
+    return (reg.sig_in_sel ? reg.in_sel : -1);
+}
+
 /**
   * @brief Force hold digital io pad.
   * @note GPIO force hold, whether the chip in sleep mode or wakeup mode.