ESP32s3 - abort panic after initialization many peripherals (IDFGH-8414)

[krzysiek-sd]

Answers checklist.

• I have read the documentation ESP-IDF Programming Guide and the issue is not addressed there.
• I have updated my IDF branch (master or release) to the latest version and checked that the issue is present there.
• I have searched the issue tracker for a similar issue and not found a similar issue.

IDF version.

v4.4.1, V4.4.2, v5.1-dev-992-gaf28c1fa21

Operating System used.

Windows

How did you build your project?

Eclipse IDE

If you are using Windows, please specify command line type.

No response

Development Kit.

ESP32-S3-DevKitC-1

Power Supply used.

USB

What is the expected behavior?

All peripherals should be initialized with no panic abort.

What is the actual behavior?

Is panic abort after initialized mcpwm module. When I put UART initialization before mcpwm then abort panic is after UART initialization.

Steps to reproduce.

I am using ESP-IDF v5.1.

Only need to run code below to cause a problem.

Debug Logs.

ELF file SHA256: fe7a80bd52551926

Rebooting...
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x3 (RTC_SW_SYS_RST),boot:0x8 (SPI_FAST_FLASH_BOOT)
Saved PC:0x40375788
0x40375788: esp_restart_noos_dig at C:/Espressif/frameworks/esp-idf/components/esp_system/esp_system.c:46 (discriminator 1)

SPIWP:0xee
mode:DIO, clock div:2
load:0x3fce3810,len:0x16ac
load:0x403c9700,len:0xbb4
load:0x403cc700,len:0x2c14
entry 0x403c9900
I (26) boot: ESP-IDF v5.1-dev-839-g29830f609d 2nd stage bootloader
I (26) boot: compile time Sep 23 2022 08:58:02
I (26) boot: chip revision: V001
I (30) boot_comm: chip revision: 1, min. bootloader chip revision: 0
I (37) boot.esp32s3: Boot SPI Speed : 40MHz
I (42) boot.esp32s3: SPI Mode       : DIO
I (47) boot.esp32s3: SPI Flash Size : 4MB
I (52) boot: Enabling RNG early entropy source...
I (57) boot: Partition Table:
I (60) boot: ## Label            Usage          Type ST Offset   Length
I (68) boot:  0 nvs              WiFi data        01 02 00009000 00006000
I (75) boot:  1 phy_init         RF data          01 01 0000f000 00001000
I (83) boot:  2 factory          factory app      00 00 00010000 00100000
I (90) boot: End of partition table
I (94) boot_comm: chip revision: 1, min. application chip revision: 0
I (101) esp_image: segment 0: paddr=00010020 vaddr=3c020020 size=0bcc4h ( 48324) map
I (122) esp_image: segment 1: paddr=0001bcec vaddr=3fc93700 size=02b58h ( 11096) load
I (126) esp_image: segment 2: paddr=0001e84c vaddr=40374000 size=017cch (  6092) load
I (130) esp_image: segment 3: paddr=00020020 vaddr=42000020 size=1db88h (121736) map
I (167) esp_image: segment 4: paddr=0003dbb0 vaddr=403757cc size=0de98h ( 56984) load
I (183) esp_image: segment 5: paddr=0004ba50 vaddr=50000000 size=00010h (    16) load
I (190) boot: Loaded app from partition at offset 0x10000
I (190) boot: Disabling RNG early entropy source...
I (193) cpu_start: Pro cpu up.
I (196) cpu_start: Starting app cpu, entry point is 0x40375314
0x40375314: call_start_cpu1 at C:/Espressif/frameworks/esp-idf/components/esp_system/port/cpu_start.c:146

I (0) cpu_start: App cpu up.
I (214) cpu_start: Pro cpu start user code
I (214) cpu_start: cpu freq: 160000000 Hz
I (214) cpu_start: Application information:
I (214) cpu_start: Project name:     uart_echo_5.0
I (214) cpu_start: App version:      1
I (215) cpu_start: Compile time:     Sep 23 2022 08:57:47
I (215) cpu_start: ELF file SHA256:  fe7a80bd52551926...
I (215) cpu_start: ESP-IDF:          v5.1-dev-839-g29830f609d
I (216) heap_init: Initializing. RAM available for dynamic allocation:
I (216) heap_init: At 3FC96CB0 len 00052A60 (330 KiB): D/IRAM
I (216) heap_init: At 3FCE9710 len 00005724 (21 KiB): STACK/DRAM
I (216) heap_init: At 3FCF0000 len 00008000 (32 KiB): DRAM
I (217) heap_init: At 600FE010 len 00001FF0 (7 KiB): RTCRAM
I (219) spi_flash: detected chip: generic
I (219) spi_flash: flash io: dio
W (219) spi_flash: Detected size(8192k) larger than the size in the binary image header(4096k). Using the size in the binary image header.
I (221) cpu_start: Starting scheduler on PRO CPU.
I (0) cpu_start: Starting scheduler on APP CPU.
I (226) gpio: GPIO[5]| InputEn: 1| OutputEn: 0| OpenDrain: 0| Pullup: 1| Pulldown: 0| Intr:0 
E (236) mcpwm: mcpwm_capture_channel_register_event_callbacks(355): install interrupt service for cap channel failed
ESP_ERROR_CHECK failed: esp_err_t 0x105 (ESP_ERR_NOT_FOUND) at 0x4200710b
0x4200710b: app_main at C:/Workspace_IDF/uart_echo_5.0/main/main.c:274 (discriminator 1)

file: "./main/main.c" line 274
func: app_main
expression: mcpwm_capture_channel_register_event_callbacks(cap_SYNCH_L_chan, &cbs_synch_L, task_synch_L)

abort() was called at PC 0x4037b49f on core 0
0x4037b49f: _esp_error_check_failed at C:/Espressif/frameworks/esp-idf/components/esp_system/esp_err.c:47



Backtrace: 0x40375dea:0x3fcf3810 0x4037b4a9:0x3fcf3830 0x40381546:0x3fcf3850 0x4037b49f:0x3fcf38c0 0x4200710b:0x3fcf38f0 0x4201d9b7:0x3fcf3a40 0x4037def1:0x3fcf3a70
0x40375dea: panic_abort at C:/Espressif/frameworks/esp-idf/components/esp_system/panic.c:417

0x4037b4a9: esp_system_abort at C:/Espressif/frameworks/esp-idf/components/esp_system/esp_system.c:135

0x40381546: abort at C:/Espressif/frameworks/esp-idf/components/newlib/abort.c:38

0x4037b49f: _esp_error_check_failed at C:/Espressif/frameworks/esp-idf/components/esp_system/esp_err.c:47

0x4200710b: app_main at C:/Workspace_IDF/uart_echo_5.0/main/main.c:274 (discriminator 1)

0x4201d9b7: main_task at C:/Espressif/frameworks/esp-idf/components/freertos/FreeRTOS-Kernel/portable/port_common.c:131 (discriminator 2)

0x4037def1: vPortTaskWrapper at C:/Espressif/frameworks/esp-idf/components/freertos/FreeRTOS-Kernel/portable/xtensa/port.c:151

More Information.

#include <stdio.h>
#include <stdbool.h>
#include <stddef.h>
#include <stdint.h>
#include "freertos/FreeRTOS.h"
#include "freertos/task.h"
#include "sdkconfig.h"
#include "esp_log.h"
#include <esp_system.h>
#include "driver/uart.h"
#include "driver/gpio.h"
#include "driver/spi_master.h"
#include "driver/i2c.h"
#include "driver/gptimer.h"
#include "hal/mcpwm_ll.h"
#include "driver/mcpwm_cap.h"

#define TIMER_FREQ 1000000 //1MHz so resolution 1us
#define SYS_TIMER_PERIOD TIMER_FREQ/1000 //1ms
#define Z_MEAS_2P_TIMER_PERIOD TIMER_FREQ/100 //100us

#define ECHO_TEST_TXD (CONFIG_EXAMPLE_UART_TXD)
#define ECHO_TEST_RXD (CONFIG_EXAMPLE_UART_RXD)
#define ECHO_TEST_RTS (UART_PIN_NO_CHANGE)
#define ECHO_TEST_CTS (UART_PIN_NO_CHANGE)

#define ECHO_UART_PORT_NUM (CONFIG_EXAMPLE_UART_PORT_NUM)
#define ECHO_UART_BAUD_RATE (CONFIG_EXAMPLE_UART_BAUD_RATE)
#define ECHO_TASK_STACK_SIZE (CONFIG_EXAMPLE_TASK_STACK_SIZE)

#define BUF_SIZE (1024)

#define SPI_ADS131A02_CLK_FREQ_HZ (1200001000) //1MHz - min stable SCLK for ADS131A02 is 25MHz

#define I2C_LCD_EXPANDER_MASTER_NUM I2C_NUM_0 /*!< I2C master i2c port number, the number of i2c peripheral interfaces available will depend on the chip /
#define I2C_LCD_EXPANDER_MASTER_FREQ_HZ 800000 /!< I2C master clock frequency */
#define I2C_LCD_EXPANDER_MASTER_SDA_IO 35
#define I2C_LCD_EXPANDER_MASTER_SCL_IO 36

#define I2C_OTHER_DEVICES_MASTER_NUM I2C_NUM_1 /*!< I2C master i2c port number, the number of i2c peripheral interfaces available will depend on the chip /
#define I2C_OTHER_DEVICES_MASTER_FREQ_HZ 10000 /!< I2C master clock frequency */
#define I2C_OTHER_DEVICES_MASTER_SDA_IO 47
#define I2C_OTHER_DEVICES_MASTER_SCL_IO 48
#define I2C_MASTER_TIMEOUT_MS 1000

#define I2C_MASTER_RX_BUF_DISABLE 0 /*!< I2C master doesn't need buffer /
#define I2C_MASTER_TX_BUF_DISABLE 0 /!< I2C master doesn't need buffer */

#define ESP_INTR_FLAG_DEFAULT 0

#define GPIO_ADC_SPI_CS 11
#define GPIO_ADC_DRDY 13
#define GPIO_SYNCH_H 4
#define GPIO_SYNCH_L 5
#define GPIO_SYNCH_V0_A 6

#define GPIO_POWER_LOCK 2
#define GPIO_POWER_BUTTON 1

static const char *TAG = "TEST";

static bool IRAM_ATTR SysTimerISRcallback(gptimer_handle_t timer, const gptimer_alarm_event_data_t *edata, void *user_data)
{
BaseType_t high_task_awoken = pdFALSE;

return high_task_awoken == pdTRUE; // return whether we need to yield at the end of ISR

}

static bool IRAM_ATTR Synch_L_isr_handler(mcpwm_cap_channel_handle_t cap_chan, const mcpwm_capture_event_data_t *edata, void *user_data)
{
bool ret = 0;

return ret;

}

static bool IRAM_ATTR Synch_H_isr_handler(mcpwm_cap_channel_handle_t cap_chan, const mcpwm_capture_event_data_t *edata, void *user_data)
{
bool ret = 0;

return ret;

}

static bool IRAM_ATTR Synch_V0_isr_handler(mcpwm_cap_channel_handle_t cap_chan, const mcpwm_capture_event_data_t *edata, void *user_data)
{
bool ret = 0;

return ret;

}

static void ADC_SetCS(void)
{
gpio_set_level(14, 1);
}

static void ADC_ClrCS(void)
{
gpio_set_level(14, 1);
}

void app_main(void)
{

//=================================== I2C init =========================================================
i2c_config_t conf;

conf.mode = I2C_MODE_MASTER;
conf.sda_io_num = I2C_LCD_EXPANDER_MASTER_SDA_IO;
conf.scl_io_num = I2C_LCD_EXPANDER_MASTER_SCL_IO;
conf.sda_pullup_en = GPIO_PULLUP_ENABLE;
conf.scl_pullup_en = GPIO_PULLUP_ENABLE;
conf.master.clk_speed = I2C_LCD_EXPANDER_MASTER_FREQ_HZ;
conf.clk_flags = 0;
i2c_param_config(I2C_LCD_EXPANDER_MASTER_NUM, &conf);
i2c_driver_install (I2C_LCD_EXPANDER_MASTER_NUM, I2C_MODE_MASTER, I2C_MASTER_RX_BUF_DISABLE, I2C_MASTER_TX_BUF_DISABLE, 0);


conf.mode = I2C_MODE_MASTER;
conf.sda_io_num = I2C_OTHER_DEVICES_MASTER_SDA_IO;
conf.scl_io_num = I2C_OTHER_DEVICES_MASTER_SCL_IO;
conf.sda_pullup_en = GPIO_PULLUP_ENABLE;
conf.scl_pullup_en = GPIO_PULLUP_ENABLE;
conf.master.clk_speed = I2C_OTHER_DEVICES_MASTER_FREQ_HZ;
conf.clk_flags = 0;
i2c_param_config(I2C_OTHER_DEVICES_MASTER_NUM, &conf);
i2c_driver_install (I2C_OTHER_DEVICES_MASTER_NUM, I2C_MODE_MASTER, I2C_MASTER_RX_BUF_DISABLE, I2C_MASTER_TX_BUF_DISABLE, 0);

//========================= GPIO init ================================

gpio_set_direction(GPIO_ADC_DRDY, GPIO_MODE_INPUT);

gpio_set_direction(GPIO_ADC_SPI_CS, GPIO_MODE_OUTPUT);
gpio_set_level(GPIO_ADC_SPI_CS, 1);

//install gpio isr service
gpio_install_isr_service(ESP_INTR_FLAG_DEFAULT);

//================================ Timer1 init ===========================

gptimer_handle_t gptimerSysTimer1 = NULL;

gptimer_config_t timer_config1 =
{
   .clk_src = GPTIMER_CLK_SRC_DEFAULT,
   .direction = GPTIMER_COUNT_UP,
   .resolution_hz = TIMER_FREQ, 			// 1MHz, 1 tick=1us
};
ESP_ERROR_CHECK(gptimer_new_timer(&timer_config1, &gptimerSysTimer1));

gptimer_event_callbacks_t cbs1 =
{
	.on_alarm = SysTimerISRcallback,
};

ESP_ERROR_CHECK(gptimer_register_event_callbacks(gptimerSysTimer1, &cbs1, NULL));

ESP_ERROR_CHECK(gptimer_enable(gptimerSysTimer1));

gptimer_alarm_config_t alarm_config1 =
{
	.alarm_count = SYS_TIMER_PERIOD, //period = 1ms
	.flags.auto_reload_on_alarm = true,
};


ESP_ERROR_CHECK(gptimer_set_alarm_action(gptimerSysTimer1, &alarm_config1));
ESP_ERROR_CHECK(gptimer_start(gptimerSysTimer1));

//================================ Timer2 init ===========================

gptimer_handle_t gptimerSysTimer2 = NULL;

gptimer_config_t timer_config2 =
{
   .clk_src = GPTIMER_CLK_SRC_DEFAULT,
   .direction = GPTIMER_COUNT_UP,
   .resolution_hz = TIMER_FREQ, 			// 1MHz, 1 tick=1us
};
ESP_ERROR_CHECK(gptimer_new_timer(&timer_config2, &gptimerSysTimer2));

gptimer_event_callbacks_t cbs2 =
{
	.on_alarm = SysTimerISRcallback,
};

ESP_ERROR_CHECK(gptimer_register_event_callbacks(gptimerSysTimer2, &cbs2, NULL));

ESP_ERROR_CHECK(gptimer_enable(gptimerSysTimer2));

gptimer_alarm_config_t alarm_config2 =
{
	.alarm_count = SYS_TIMER_PERIOD, //period = 1ms
	.flags.auto_reload_on_alarm = true,
};

ESP_ERROR_CHECK(gptimer_set_alarm_action(gptimerSysTimer2, &alarm_config2));

//============================== SPI init ========================================

spi_device_handle_t ADS131A02Spi2DeviceHandle;    ///< SPI2 device handle

spi_bus_config_t spiBusConf =			//this kind of initialization clear other values in structure
{
	.miso_io_num = 10,
	.mosi_io_num = 11,
	.sclk_io_num = 12,
	.quadwp_io_num = -1,
	.quadhd_io_num = -1,
	.max_transfer_sz = 32,
};

spi_bus_initialize(SPI2_HOST, &spiBusConf, SPI_DMA_CH_AUTO);

spi_device_interface_config_t spiDevConf =
{
	.command_bits = 0,
	.clock_speed_hz = SPI_ADS131A02_CLK_FREQ_HZ,
	.mode = 1,	//SPI mode 1 => CPOL = 0, CPHA = 1
	.spics_io_num = -1,
	.queue_size = 1,
	.flags = SPI_DEVICE_NO_DUMMY,
	.pre_cb =  (void*)ADC_ClrCS,			//cs_high,
	.post_cb = (void*)ADC_SetCS,			//cs_low,
	.input_delay_ns = 0,//SPI_ADS131A02_INPUT_DELAY_NS,  //the EEPROM output the data half a SPI clock behind - nie wiem czy to potrzebne
};

spi_bus_add_device(SPI2_HOST, &spiDevConf, &ADS131A02Spi2DeviceHandle);

//=================================== Capture init ========================================

mcpwm_capture_channel_config_t conf_SYNCH_L = {0};
mcpwm_capture_channel_config_t conf_SYNCH_H = {0};
mcpwm_capture_channel_config_t conf_SYNCH_V0 = {0};

mcpwm_cap_timer_handle_t cap_timer = NULL;
mcpwm_capture_timer_config_t cap_conf = {
    .clk_src = MCPWM_CAPTURE_CLK_SRC_DEFAULT,
    .group_id = 0,
};

mcpwm_cap_channel_handle_t cap_SYNCH_L_chan = NULL;
mcpwm_cap_channel_handle_t cap_SYNCH_H_chan = NULL;
mcpwm_cap_channel_handle_t cap_SYNCH_V0_chan = NULL;

ESP_ERROR_CHECK(mcpwm_new_capture_timer(&cap_conf, &cap_timer));

//---------------------------- set CAP_0 on GPIO_SYNCH_L ---------------------------------
conf_SYNCH_L.gpio_num = GPIO_SYNCH_L;
conf_SYNCH_L.prescale = 1;
conf_SYNCH_L.flags.neg_edge = false;
conf_SYNCH_L.flags.pos_edge = true;
conf_SYNCH_L.flags.pull_up = true;
conf_SYNCH_L.flags.pull_down = false;

ESP_ERROR_CHECK(mcpwm_new_capture_channel(cap_timer, &conf_SYNCH_L, &cap_SYNCH_L_chan));

TaskHandle_t task_synch_L = xTaskGetCurrentTaskHandle();

mcpwm_capture_event_callbacks_t cbs_synch_L =
{
	.on_cap = Synch_L_isr_handler,
};

ESP_ERROR_CHECK(mcpwm_capture_channel_register_event_callbacks(cap_SYNCH_L_chan, &cbs_synch_L, task_synch_L));
//-------------------------------------------------------------------------------------------------

//---------------------------- set CAP_1 on GPIO_SYNCH_H -------------------------------------
conf_SYNCH_H.gpio_num = GPIO_SYNCH_H;
conf_SYNCH_H.prescale = 1;
conf_SYNCH_H.flags.neg_edge = false;
conf_SYNCH_H.flags.pos_edge = true;
conf_SYNCH_H.flags.pull_up = true;
conf_SYNCH_H.flags.pull_down = false;

ESP_ERROR_CHECK(mcpwm_new_capture_channel(cap_timer, &conf_SYNCH_H, &cap_SYNCH_H_chan));

mcpwm_capture_event_callbacks_t cbs_synch_H =
{
	.on_cap = Synch_H_isr_handler,
};

ESP_ERROR_CHECK(mcpwm_capture_channel_register_event_callbacks(cap_SYNCH_H_chan, &cbs_synch_H, NULL));
//-------------------------------------------------------------------------------------------------

//----------------------------- set CAP_2 on GPIO_SYNCH_V0 --------------------------------------
conf_SYNCH_V0.gpio_num = GPIO_SYNCH_V0_A;
conf_SYNCH_V0.prescale = 1;
conf_SYNCH_V0.flags.neg_edge = false;
conf_SYNCH_V0.flags.pos_edge = true;
conf_SYNCH_V0.flags.pull_up = true;
conf_SYNCH_V0.flags.pull_down = false;

ESP_ERROR_CHECK(mcpwm_new_capture_channel(cap_timer, &conf_SYNCH_V0, &cap_SYNCH_V0_chan));

mcpwm_capture_event_callbacks_t cbs_synch_V0 =
{
	.on_cap = Synch_V0_isr_handler,
};

ESP_ERROR_CHECK(mcpwm_capture_channel_register_event_callbacks(cap_SYNCH_V0_chan, &cbs_synch_V0, NULL));
//-------------------------------------------------------------------------------------------------

ESP_ERROR_CHECK(mcpwm_capture_timer_enable(cap_timer));
ESP_ERROR_CHECK(mcpwm_capture_timer_start(cap_timer));

//=======================================================================================================

while(1)
{
	ESP_LOGI(TAG, "Tick 500");
	vTaskDelay(pdMS_TO_TICKS(500));
	taskYIELD();
}

//===================================== UART init ==========================================================

uart_config_t uart_config =
{
	.baud_rate = ECHO_UART_BAUD_RATE,
	.data_bits = UART_DATA_8_BITS,
	.parity    = UART_PARITY_DISABLE,
	.stop_bits = UART_STOP_BITS_1,
	.flow_ctrl = UART_HW_FLOWCTRL_DISABLE,
	.source_clk = UART_SCLK_DEFAULT,
};
int intr_alloc_flags = 0;

#if CONFIG_UART_ISR_IN_IRAM
    intr_alloc_flags = ESP_INTR_FLAG_IRAM;
#endif

ESP_ERROR_CHECK(uart_driver_install(ECHO_UART_PORT_NUM, BUF_SIZE * 2, 0, 0, NULL, intr_alloc_flags));
ESP_ERROR_CHECK(uart_param_config(ECHO_UART_PORT_NUM, &uart_config));
ESP_ERROR_CHECK(uart_set_pin(ECHO_UART_PORT_NUM, ECHO_TEST_TXD, ECHO_TEST_RXD, ECHO_TEST_RTS, ECHO_TEST_CTS));

while(1)
{
	ESP_LOGI(TAG, "Tick 500");
	vTaskDelay(pdMS_TO_TICKS(500));
	taskYIELD();
}

//=======================================================================================================

}

You can find a link to my project below.
https://github.com/krzysiek-sd/ESP32-S3

[igrr]

Hi @krzysiek-sd,
It looks like you are running out of the available Level 1 interrupts. You can modify your code to pass intr_alloc_flags argument equal to ESP_INTR_FLAG_LOWMED, instead of 0 or ESP_INTR_FLAG_DEFAULT.

For example,
i2c_driver_install(..., ESP_INTR_FLAG_LOWMED) instead of i2c_driver_install(..., 0), and so on.

Additionally, for some peripherals (like I2C and GPIO), you can share the CPU interrupt. This helps reduce the total number of CPU interrupts your code needs. To do this, use ESP_INTR_FLAG_SHARED flag.

For more information, please check the interrupt allocation docs: https://docs.espressif.com/projects/esp-idf/en/latest/esp32s3/api-reference/system/intr_alloc.html

[igrr]

I'm going to close the issue, please feel free to leave another comment if you still have this problem.