Refactor SDC to avoid VPR net aliases. #1321
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This change somehow caused chipsalliance/yosys-f4pga-plugins#8, unclear why. |
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
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This is a workaround for the VPR bug between SDC constraints and net aliases for the DDR uart test, until VPR is fixed.