Assessment of the difficulty in porting CPU architecture for fftw3

[wangyuliu]

Hello everyone! I am working on implementing a tool to assess the complexity of CPU architecture porting. It primarily focuses on RISC-V architecture porting. As part of my dataset, I have collected the fftw3 project. I would like to gather community opinions to support my assessment. I appreciate your help and response! Based on scanning tools, the porting complexity is determined to be moderate leaning towards simple, with a small amount of code related to the CPU architecture in the project. It would require professional developers, but not a large-scale team, to handle this task (referring to the overall workload from adapting the project to a specific architecture to achieving full functionality on that architecture). Is this assessment accurate? I look forward to your help and response.
各位网友大家好啊~~~~我正在实施一个工具，以评估CPU架构移植的复杂性。它主要关注RISC-V体系结构的移植。作为我的数据集的一部分，我收集了fftw3项目。我希望收集社会人士的意见，以支持我的评估。我很感谢你的帮助和回应！基于扫描工具，移植的复杂性被确定为中等，与项目中的CPU架构相关的代码量适中。这将需要一个专业的团队，但不是一个大规模的团队，来处理这个任务（指的是从使项目适应特定架构到在该架构上实现全部功能的总体工作量）。这样的评价准确吗？我期待着你的帮助和回应。

[rdolbeau]

Porting to a new architecture already supported by the build system (configure, etc.) it usually limited to the need for an accurate timing source - the more precise, the better. That's for functionality.

Performance may require to also implement some dedicated SIMD support. For RISC-V the work is ongoing.