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Northeast University
- ShenYang
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ascon-verilog
ascon-verilog PublicForked from rprimas/ascon-verilog
Verilog Hardware Design of Ascon v1.2
SystemVerilog
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cdma_accelerator
cdma_accelerator PublicForked from Hyunho-Won/cdma_accelerator
这个不错,学完CDMA可以再做个这个
Verilog
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USTC-RVSoC
USTC-RVSoC PublicForked from WangXuan95/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC,包含一个简单且可扩展的外设总线。
SystemVerilog
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