Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Mill support for Chisel3 #1035

Merged
merged 22 commits into from Mar 20, 2019
Merged

Mill support for Chisel3 #1035

merged 22 commits into from Mar 20, 2019

Conversation

edwardcwang
Copy link
Contributor

Type of change: feature

Impact: no functional change

Development Phase: implementation

Release Notes: Support mill in Chisel3.

jackkoenig and others added 20 commits April 26, 2018 13:15
* Change VerilogMemDelays to put new Statements at end of Module

Fixes #547

This is instead of putting them right after the modified DefMemory which could
result in use before declaration errors for things that feed into the new
logic.

* Adds tests that show VerilogMemDelays crashing. (#792)
Still some problems building source and doc jars, largely due to relative paths.
 - need to specify mainClass - mill should figure it out on its own
 - manifest isn't complete
 - javaDoc is missing version info, some javascript, and differs from sbt generated javaDoc, but it doesn include core and internal documentation
 - ivys are missing description, configurations, scala dependencies
 - poms use artifactId for name (instead of descrption), license is BSD-3-Clause, developer is missing url, dependencies are missing scala dependencies, but include a dependency on the library itself(!).
Move common code into CommonBuild.sc
Remove extra ThisBuildInfo trait
Override publishXmlDeps() to avoid generating a self-dependency (since our dependent modules don't really have their own identity and end up duplicating PublishChiselModule
@edwardcwang edwardcwang added the Squash and merge These commits don't matter, squash and merge label Mar 15, 2019
@edwardcwang edwardcwang requested a review from ucbjrl March 15, 2019 20:50
@edwardcwang edwardcwang requested a review from a team as a code owner March 15, 2019 20:50
Copy link
Contributor

@ucbjrl ucbjrl left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Looks pretty good @edwardcwang. I'm getting test failures with the make mill.test.all target. I'm trying to sort that out.

Copy link
Contributor

@ucbjrl ucbjrl left a comment

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I edited the Makefile to fetch the official mill-0.3.5, and edited build.sc to use the same Scala versions as sbt does. If you're happy with these changes, go ahead and commit this.

@edwardcwang
Copy link
Contributor Author

@ucbjrl Thank you so much for looking into this! Let me test this out and I'll get back to you.

@edwardcwang
Copy link
Contributor Author

This appears to work; will go ahead and squash-merge this.

@edwardcwang edwardcwang merged commit 1894319 into master Mar 20, 2019
@edwardcwang edwardcwang deleted the mill branch March 20, 2019 17:06
@sequencer sequencer mentioned this pull request Feb 7, 2020
jackkoenig pushed a commit that referenced this pull request Feb 28, 2023
…ng. (#1035)

* Add --nodedup option to facilitate FIRRTL to verilog regression testing.

* Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
Squash and merge These commits don't matter, squash and merge
Projects
None yet
Development

Successfully merging this pull request may close these issues.

None yet

3 participants