"shouldn't get here" in RemoveCHIRRTL

[aswaterman]

circuit Test :
  module Test :
    input clock : Clock

    cmem rf : UInt<64>[31]
    node rf_wdata = mux(UInt(0), UInt(0), UInt(0))
    infer mport port = rf[UInt(0)], clock
    port <- rf_wdata

results in

Exception in thread "main" firrtl.FIRRTLException: shouldn't be here
at firrtl.Utils$.error(Utils.scala:204)
at firrtl.Utils$.get_valid_points(Utils.scala:241)
at firrtl.passes.RemoveCHIRRTL$.remove_chirrtl_s(RemoveCHIRRTL.scala:229)
at firrtl.passes.RemoveCHIRRTL$$anonfun$remove_chirrtl_s$3.apply(RemoveCHIRRTL.scala:238)
at firrtl.passes.RemoveCHIRRTL$$anonfun$remove_chirrtl_s$3.apply(RemoveCHIRRTL.scala:238)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
at scala.collection.TraversableLike$class.map(TraversableLike.scala:245)
at scala.collection.AbstractTraversable.map(Traversable.scala:104)
at firrtl.ir.Block.mapStmt(IR.scala:227)
at firrtl.Mappers$StmtMagnet$$anon$4.map(Mappers.scala:41)
at firrtl.Mappers$StmtMap$.map$extension(Mappers.scala:55)
at firrtl.passes.RemoveCHIRRTL$.remove_chirrtl_s(RemoveCHIRRTL.scala:238)
at firrtl.passes.RemoveCHIRRTL$$anonfun$remove_chirrtl_m$5.apply(RemoveCHIRRTL.scala:250)
at firrtl.passes.RemoveCHIRRTL$$anonfun$remove_chirrtl_m$5.apply(RemoveCHIRRTL.scala:250)
at firrtl.ir.Module.mapStmt(IR.scala:433)
at firrtl.Mappers$ModuleMagnet$$anon$11.map(Mappers.scala:115)
at firrtl.Mappers$ModuleMap$.map$extension(Mappers.scala:125)
at firrtl.passes.RemoveCHIRRTL$.remove_chirrtl_m(RemoveCHIRRTL.scala:250)
at firrtl.passes.RemoveCHIRRTL$$anonfun$10.apply(RemoveCHIRRTL.scala:254)
at firrtl.passes.RemoveCHIRRTL$$anonfun$10.apply(RemoveCHIRRTL.scala:254)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
at scala.collection.mutable.ResizableArray$class.foreach(ResizableArray.scala:59)
at scala.collection.mutable.ArrayBuffer.foreach(ArrayBuffer.scala:48)
at scala.collection.TraversableLike$class.map(TraversableLike.scala:245)
at scala.collection.AbstractTraversable.map(Traversable.scala:104)
at firrtl.passes.RemoveCHIRRTL$.run(RemoveCHIRRTL.scala:254)
at firrtl.SimpleRun$$anonfun$1$$anonfun$2.apply(LoweringCompilers.scala:47)
at firrtl.SimpleRun$$anonfun$1$$anonfun$2.apply(LoweringCompilers.scala:47)
at firrtl.Utils$.time(Utils.scala:55)
at firrtl.SimpleRun$$anonfun$1.apply(LoweringCompilers.scala:47)
at firrtl.SimpleRun$$anonfun$1.apply(LoweringCompilers.scala:45)
at scala.collection.LinearSeqOptimized$class.foldLeft(LinearSeqOptimized.scala:124)
at scala.collection.immutable.List.foldLeft(List.scala:84)
at firrtl.SimpleRun$class.run(LoweringCompilers.scala:45)
at firrtl.Chisel3ToHighFirrtl.run(LoweringCompilers.scala:61)
at firrtl.Chisel3ToHighFirrtl.execute(LoweringCompilers.scala:68)
at firrtl.Compiler$$anonfun$compile$1.apply(Compiler.scala:71)
at firrtl.Compiler$$anonfun$compile$1.apply(Compiler.scala:70)
at scala.collection.LinearSeqOptimized$class.foldLeft(LinearSeqOptimized.scala:124)
at scala.collection.immutable.List.foldLeft(List.scala:84)
at firrtl.Compiler$class.compile(Compiler.scala:70)
at firrtl.VerilogCompiler.compile(LoweringCompilers.scala:198)
at firrtl.Driver$.compile(Driver.scala:109)
at firrtl.Driver$.run(Driver.scala:183)
at firrtl.Driver$.main(Driver.scala:86)
at firrtl.Driver.main(Driver.scala)